Technical Sessions

This session presents recent advances in highly integrated RF transceiver and beamforming architectures that enable next-generation wireless infrastructure and high-resolution sensing. The talks span a wide range of mm-wave applications, including a 57–67GHz four-channel transmitter with fine-resolution phase shifting and built-in self-test for Doppler-offset FMCW radar, a high-linearity K-band multi-beam transmitter IC targeting LEO SATCOM, and a high-power SiGe TXSIP delivering more than 32dBm across the 71–86GHz E-band for point-to-point backhaul. Complementing these mm-wave front-ends, the session also features a single-chip ORAN-compliant 4TX-4RX 5G radio-unit transceiver that bridges Ethernet to RF for compact, power-efficient base-station deployments.

This session features four papers on high-performance Ku- and Ka-band CMOS oscillators utilizing innovative architectures including: triple-tank resonators for flicker-noise suppression; area-efficient Gm boosted cores; series-resonance tank with 3rd harmonic extraction; and quad-mode inductive switching. These designs achieve high figures-of-merit and ultra-wide tuning ranges across a frequency span of 9.9 to 30GHz, addressing key challenges in next-generation frequency synthesis.

This session highlights circuit techniques that advance fully digital PAs and transmitters toward higher output power, broader bandwidth, and cleaner spectra. It begins with a reconfigurable multi-standard IoT digital transmitter using IQ-shared PA. Next, a 28.5dBm all-digital Wi-Fi 7 polar transmitter employing triple-stacked class-G Doherty PA is demonstrated. The third paper presents a Wi-Fi Doherty polar transmitter that suppresses out-of-channel noise using a mixed-domain FIR technique. The session concludes with a wideband RF power DAC achieving -47.2dB EVM.

The future of computing requires innovations in connectivity and architectures that can solve complex problems. This session presents novel components that enable the next wave of high-speed connectivity solutions to meet today's significant compute demand. Innovative wide-band circuit components driven by new technologies such as phase-change materials and high-speed NPN-PNP bipolar transistor architecture will be presented. In addition, the session showcases a high-speed galvanically isolated data link. Finally, a cryogenic controller for color centers in diamond will be introduced to enable scalable quantum computing and networking.

This session presents recent advances in highly integrated RF transceiver and beamforming architectures that enable next-generation wireless infrastructure and high-resolution sensing. The talks span a wide range of mm-wave applications, including a 57–67GHz four-channel transmitter with fine-resolution phase shifting and built-in self-test for Doppler-offset FMCW radar, a high-linearity K-band multi-beam transmitter IC targeting LEO SATCOM, and a high-power SiGe TXSIP delivering more than 32dBm across the 71–86GHz E-band for point-to-point backhaul. Complementing these mm-wave front-ends, the session also features a single-chip ORAN-compliant 4TX-4RX 5G radio-unit transceiver that bridges Ethernet to RF for compact, power-efficient base-station deployments.

This session features four papers on high-performance Ku- and Ka-band CMOS oscillators utilizing innovative architectures including: triple-tank resonators for flicker-noise suppression; area-efficient Gm boosted cores; series-resonance tank with 3rd harmonic extraction; and quad-mode inductive switching. These designs achieve high figures-of-merit and ultra-wide tuning ranges across a frequency span of 9.9 to 30GHz, addressing key challenges in next-generation frequency synthesis.

This session highlights circuit techniques that advance fully digital PAs and transmitters toward higher output power, broader bandwidth, and cleaner spectra. It begins with a reconfigurable multi-standard IoT digital transmitter using IQ-shared PA. Next, a 28.5dBm all-digital Wi-Fi 7 polar transmitter employing triple-stacked class-G Doherty PA is demonstrated. The third paper presents a Wi-Fi Doherty polar transmitter that suppresses out-of-channel noise using a mixed-domain FIR technique. The session concludes with a wideband RF power DAC achieving -47.2dB EVM.

The future of computing requires innovations in connectivity and architectures that can solve complex problems. This session presents novel components that enable the next wave of high-speed connectivity solutions to meet today's significant compute demand. Innovative wide-band circuit components driven by new technologies such as phase-change materials and high-speed NPN-PNP bipolar transistor architecture will be presented. In addition, the session showcases a high-speed galvanically isolated data link. Finally, a cryogenic controller for color centers in diamond will be introduced to enable scalable quantum computing and networking.

This session highlights state-of-the-art mm-wave and sub-THz transmitters and receivers, spanning a heterogeneously integrated InP-FinFET CMOS sliding-IF transmitter, a packaged InP HBT transceiver module, emerging direct digital demodulation architectures, advanced glass/antenna-in-package integration, a D-band receiver with injection-locking-based quadrature correction, and a 28nm CMOS transceiver enabling Dielectric Waveguide (DWG) communication.

This session presents advanced CMOS frequency-generation circuits, including a D-band self calibrated quadrature generator, two E-band low-phase-noise LO with quadrature calibration and with harmonic extraction, and a series resonance 40GHz VCO.

This session highlights recent advances in LEO SATCOM and FR3 transmitter front-ends and power amplifiers, covering devices, circuits, packaging, and design automation. The first paper demonstrates a high-power, high-efficiency complementary BiCMOS PA using both high-speed NPN and PNP devices. The second introduces a Ka-band 4-element beamforming transmitter front-end for LEO ground terminals with a negative-feedback-based interstage matching network. The third presents a compact, watt-level, thermally robust BiCMOS flip-chip PA module for SATCOM transmit front-ends. The final paper showcases a fast specs-to-silicon mm-wave RFIC design framework using AI-assisted specs-to-layout with layout-to-silicon constraint integration.

This session highlights state-of-the-art mm-wave and sub-THz transmitters and receivers, spanning a heterogeneously integrated InP-FinFET CMOS sliding-IF transmitter, a packaged InP HBT transceiver module, emerging direct digital demodulation architectures, advanced glass/antenna-in-package integration, a D-band receiver with injection-locking-based quadrature correction, and a 28nm CMOS transceiver enabling Dielectric Waveguide (DWG) communication.

This session presents advanced CMOS frequency-generation circuits, including a D-band self calibrated quadrature generator, two E-band low-phase-noise LO with quadrature calibration and with harmonic extraction, and a series resonance 40GHz VCO.

This session highlights recent advances in LEO SATCOM and FR3 transmitter front-ends and power amplifiers, covering devices, circuits, packaging, and design automation. The first paper demonstrates a high-power, high-efficiency complementary BiCMOS PA using both high-speed NPN and PNP devices. The second introduces a Ka-band 4-element beamforming transmitter front-end for LEO ground terminals with a negative-feedback-based interstage matching network. The third presents a compact, watt-level, thermally robust BiCMOS flip-chip PA module for SATCOM transmit front-ends. The final paper showcases a fast specs-to-silicon mm-wave RFIC design framework using AI-assisted specs-to-layout with layout-to-silicon constraint integration.

The broadband circuit performance is critical for high-data-rate communications and to cover different frequency bands. In this session, various design techniques on broadband RF amplifiers and switches are introduced. For RF amplifiers, in addition to distributed topologies, a reconfigurable architecture is adopted. As for RF switches, a distributed structure as well as power combining is illustrated. These papers demonstrate the state-of-the-art performance for broadband operations.

This session presents cutting-edge advances in frequency conversion and filtering for wireless receivers, spanning FR3 to W-band frequencies. Featured papers introduce novel circuit architectures, including passive mixer-first diplexers, subharmonic mixers, and switched-Gm topologies, all optimized for high linearity and low noise. These works collectively push the performance boundaries of integrated front-ends for next-generation communication systems.

This technical session highlights state-of-the-art Power Amplifier (PA) architectures for D-band and mm-wave applications in bulk CMOS and FD-SOI. Key innovations include a D-band variable-gain PA using Guanella transformers for 36% Fractional Bandwidth (FBW) and 20Gb/s 16-QAM signaling, alongside ultra-compact 145GHz PAs featuring adaptive back-gate biasing and diode-based linearization. Ultra-broadband performance is showcased through a 9.5–40GHz linear PA utilizing compensated coupled-line transformers (126.5% FBW) and a 15.5–46.0GHz PA with high-efficiency matching networks. Finally, a 40GHz load-isolated Doherty PA is presented, offering enhanced VSWR resiliency and high efficiency for robust, high-speed wireless communication.

The broadband circuit performance is critical for high-data-rate communications and to cover different frequency bands. In this session, various design techniques on broadband RF amplifiers and switches are introduced. For RF amplifiers, in addition to distributed topologies, a reconfigurable architecture is adopted. As for RF switches, a distributed structure as well as power combining is illustrated. These papers demonstrate the state-of-the-art performance for broadband operations.

This session presents cutting-edge advances in frequency conversion and filtering for wireless receivers, spanning FR3 to W-band frequencies. Featured papers introduce novel circuit architectures, including passive mixer-first diplexers, subharmonic mixers, and switched-Gm topologies, all optimized for high linearity and low noise. These works collectively push the performance boundaries of integrated front-ends for next-generation communication systems.

This technical session highlights state-of-the-art Power Amplifier (PA) architectures for D-band and mm-wave applications in bulk CMOS and FD-SOI. Key innovations include a D-band variable-gain PA using Guanella transformers for 36% Fractional Bandwidth (FBW) and 20Gb/s 16-QAM signaling, alongside ultra-compact 145GHz PAs featuring adaptive back-gate biasing and diode-based linearization. Ultra-broadband performance is showcased through a 9.5–40GHz linear PA utilizing compensated coupled-line transformers (126.5% FBW) and a 15.5–46.0GHz PA with high-efficiency matching networks. Finally, a 40GHz load-isolated Doherty PA is presented, offering enhanced VSWR resiliency and high efficiency for robust, high-speed wireless communication.

This session highlights advances in integrated RF sensing and radars. The first paper presents a 16-VRX radar using analog I/Q correlators with state-of-the-art efficiency. The next paper discusses a 2 to 20GHz RF signal processor based on a looped phase–time array that enhances frequency resolution. The third paper presents a 405GHz 2×2 scalable transceiver with increased frequency locking range. The fourth paper presents a radar transceiver featuring a hybrid Doppler-CW/PMCW operation to achieve unambiguous range accuracy of tens of µm. Finally, a W-band PMCW transmitter using an RWTO and edge combiner concludes the session.

The front-ends and LNAs are essential building blocks of modern transceivers. The session presents a mm-wave novel self-synchronizing receiver array, a high-efficiency FR2 transmit front-end, a cryo LNA, a FR3 LNA and a mm-wave LNA exploiting noise cancelling.

This session will present new design techniques for sub-THz power amplifiers to achieve high output power, wide bandwidth, and compact chip area. This session will also present a compact, high-gain sub-THz bidirectional amplifier.

Low RMS-error and broadband phase shifters are essential building blocks for beamforming. This session features four broadband phase shifters spanning 8–110GHz, 91–125GHz, 8–28GHz, and 24–30GHz, all implemented in silicon (22nm and 65nm CMOS/FD-SOI). Highlights include a 10-bit distributed vector-summing PS with <0.22dB RMS gain error and <1.99° RMS phase error, a 91–125GHz beamforming receive channel with sub-dB gain and sub-few-degree phase error, a wideband all-passive variable gain phase shifter with calibration-free gain control, and a compact 7-bit passive hybrid achieving <1.1°/<0.61dB RMS errors. Also included is a bi-directional reflection-amplifier phase shifter for ultra-low-power RIS enabling large-scale beyond-5G deployments.

This session highlights advances in integrated RF sensing and radars. The first paper presents a 16-VRX radar using analog I/Q correlators with state-of-the-art efficiency. The next paper discusses a 2 to 20GHz RF signal processor based on a looped phase–time array that enhances frequency resolution. The third paper presents a 405GHz 2×2 scalable transceiver with increased frequency locking range. The fourth paper presents a radar transceiver featuring a hybrid Doppler-CW/PMCW operation to achieve unambiguous range accuracy of tens of µm. Finally, a W-band PMCW transmitter using an RWTO and edge combiner concludes the session.

The front-ends and LNAs are essential building blocks of modern transceivers. The session presents a mm-wave novel self-synchronizing receiver array, a high-efficiency FR2 transmit front-end, a cryo LNA, a FR3 LNA and a mm-wave LNA exploiting noise cancelling.

This session will present new design techniques for sub-THz power amplifiers to achieve high output power, wide bandwidth, and compact chip area. This session will also present a compact, high-gain sub-THz bidirectional amplifier.

Low RMS-error and broadband phase shifters are essential building blocks for beamforming. This session features four broadband phase shifters spanning 8–110GHz, 91–125GHz, 8–28GHz, and 24–30GHz, all implemented in silicon (22nm and 65nm CMOS/FD-SOI). Highlights include a 10-bit distributed vector-summing PS with <0.22dB RMS gain error and <1.99° RMS phase error, a 91–125GHz beamforming receive channel with sub-dB gain and sub-few-degree phase error, a wideband all-passive variable gain phase shifter with calibration-free gain control, and a compact 7-bit passive hybrid achieving <1.1°/<0.61dB RMS errors. Also included is a bi-directional reflection-amplifier phase shifter for ultra-low-power RIS enabling large-scale beyond-5G deployments.

The session features both radars and UWB transceivers from the industry. The FMCW radars include BIST solutions for 60GHz MIMO radar SoCs and coded MIMO transceivers designed for 76–81GHz, and an integrated 77GHz radar with in-package antenna launchers for automotive applications. The session also covers UWB receivers for IEEE 802.15.4ab, narrowband-assisted architectures resilient to blockers, and innovative techniques for achieving PVT-robust signal strength estimation.

This session presents advanced frequency multiplication techniques for signal generation from 100 to 310GHz in CMOS and SiGe technologies. The papers demonstrate phase-aligned harmonic recombination, coupled-line-based output matching, amplifier–multiplier chains, and coherent power combining to enhance efficiency, output power, bandwidth, and harmonic suppression. Reported results include up to 16dBm output power, +26.5dBm EIRP, and >70dBc harmonic rejection. Together, these works illustrate scalable circuit strategies for high-purity, high-power D-band and sub-THz transmitters suitable for emerging communication and sensing applications.

Integrated transmit/receive front-ends are rapidly expanding in capability across radar imaging, 5G/6G MIMO, SATCOM phased arrays, and wideband beamforming. This session highlights mm-wave and wideband Tx/Rx architectures that advance calibration accuracy, scalable spatial combining, and packaging-aware integration. Featured designs include a W-band FMCW radar transceiver using a self-calibrated Type-III ADPLL for 1.27cm range-resolution imaging, a compact 28GHz fully-connected Gm-cell-grid MIMO receiver network, a K-band multi-beam phased-array transmitter enabled by silicon-assisted beam combining in a 5-layer PCB, a 2–18GHz 4-channel CMOS T/R beamformer and, a 256-element 28GHz wirelessly-powered active relay transceiver with TDD-sync-free bidirectional amplifiers for robust high-capacity links.

Next-generation optical interconnects must achieve 200G/400G data rates per lane to support future intra-datacenter requirements. This session showcases high-performance optical transmitter and receiver building blocks engineered to meet these scaling demands. Presentations will cover a diverse range of cutting-edge material platforms and processes, including SiGe, CMOS, Thin-Film Lithium Niobate (TFLN), and InP, highlighting their roles in achieving the necessary power efficiency and signal integrity for the next era of data centers.

The session features both radars and UWB transceivers from the industry. The FMCW radars include BIST solutions for 60GHz MIMO radar SoCs and coded MIMO transceivers designed for 76–81GHz, and an integrated 77GHz radar with in-package antenna launchers for automotive applications. The session also covers UWB receivers for IEEE 802.15.4ab, narrowband-assisted architectures resilient to blockers, and innovative techniques for achieving PVT-robust signal strength estimation.

This session presents advanced frequency multiplication techniques for signal generation from 100 to 310GHz in CMOS and SiGe technologies. The papers demonstrate phase-aligned harmonic recombination, coupled-line-based output matching, amplifier–multiplier chains, and coherent power combining to enhance efficiency, output power, bandwidth, and harmonic suppression. Reported results include up to 16dBm output power, +26.5dBm EIRP, and >70dBc harmonic rejection. Together, these works illustrate scalable circuit strategies for high-purity, high-power D-band and sub-THz transmitters suitable for emerging communication and sensing applications.

Integrated transmit/receive front-ends are rapidly expanding in capability across radar imaging, 5G/6G MIMO, SATCOM phased arrays, and wideband beamforming. This session highlights mm-wave and wideband Tx/Rx architectures that advance calibration accuracy, scalable spatial combining, and packaging-aware integration. Featured designs include a W-band FMCW radar transceiver using a self-calibrated Type-III ADPLL for 1.27cm range-resolution imaging, a compact 28GHz fully-connected Gm-cell-grid MIMO receiver network, a K-band multi-beam phased-array transmitter enabled by silicon-assisted beam combining in a 5-layer PCB, a 2–18GHz 4-channel CMOS T/R beamformer and, a 256-element 28GHz wirelessly-powered active relay transceiver with TDD-sync-free bidirectional amplifiers for robust high-capacity links.

Next-generation optical interconnects must achieve 200G/400G data rates per lane to support future intra-datacenter requirements. This session showcases high-performance optical transmitter and receiver building blocks engineered to meet these scaling demands. Presentations will cover a diverse range of cutting-edge material platforms and processes, including SiGe, CMOS, Thin-Film Lithium Niobate (TFLN), and InP, highlighting their roles in achieving the necessary power efficiency and signal integrity for the next era of data centers.

This session showcases recent innovations in RF front-end design from across the industry that enable the performance, bandwidth, and integration demands of emerging wireless standards. The talks highlight breakthroughs in low-noise amplification, switching, and frequency generation across CMOS, SiGe, and SOI technologies. Topics include N-path receiver architectures optimized for WiFi 7 multi-link operation, high-gain D-band LNAs, power-efficient mm-wave LNAs for 5G applications, broadband frequency doublers in advanced SiGe processes, and fully differential DC-capable RF switching solutions. Together, these contributions showcase state-of-the-art techniques that push the limits of noise performance, linearity, bandwidth, and integration in modern RF systems.

This session explores cutting-edge clock generation architectures achieving sub-30fs jitter and superior spur suppression. The first paper introduces an 8–28GHz DLL with nested feedback to overcome inverter delay limits. The second paper demonstrates a 6.2GHz sampling PLL with 18.2fsrms jitter using bottom-plate sampling. The third paper describes a fractional-N digital PLL reaching 25.4fs jitter via a series-resonance DCO and power-gated oscillator. The fourth paper presents a ring-oscillator clock multiplier using a reference quadrupler for enhanced noise suppression. Finally, the last paper details a 5GHz ring-oscillator PLL employing over-sampling feedforward cancellation for a record -267.05dB FoM.

This session showcases enabling circuit blocks for next-generation sub-THz transceivers. The talks span key front-end functions such as attenuation, low-noise amplification, frequency generation, and phase shifter, targeting wideband operation and robust performance across process, voltage, and temperature.

Emerging AI workloads demand an exponential increase in XPU and switch scale-up interconnect bandwidth, alongside high-density die-to-die interfaces. This session explores novel Co-Packaged Optics (CPO) link architectures designed to meet these challenges. Presentations will highlight the use of Micro-Ring Modulators (MRM) and the enhancement of bandwidth through ultra-low-power coherent optics. Key technical deep-dives include UCIe-inspired clock-forwarding and the development of compact, power-efficient building blocks, featuring innovative Phase Interpolator (PI) designs.

This session showcases recent innovations in RF front-end design from across the industry that enable the performance, bandwidth, and integration demands of emerging wireless standards. The talks highlight breakthroughs in low-noise amplification, switching, and frequency generation across CMOS, SiGe, and SOI technologies. Topics include N-path receiver architectures optimized for WiFi 7 multi-link operation, high-gain D-band LNAs, power-efficient mm-wave LNAs for 5G applications, broadband frequency doublers in advanced SiGe processes, and fully differential DC-capable RF switching solutions. Together, these contributions showcase state-of-the-art techniques that push the limits of noise performance, linearity, bandwidth, and integration in modern RF systems.

This session explores cutting-edge clock generation architectures achieving sub-30fs jitter and superior spur suppression. The first paper introduces an 8–28GHz DLL with nested feedback to overcome inverter delay limits. The second paper demonstrates a 6.2GHz sampling PLL with 18.2fsrms jitter using bottom-plate sampling. The third paper describes a fractional-N digital PLL reaching 25.4fs jitter via a series-resonance DCO and power-gated oscillator. The fourth paper presents a ring-oscillator clock multiplier using a reference quadrupler for enhanced noise suppression. Finally, the last paper details a 5GHz ring-oscillator PLL employing over-sampling feedforward cancellation for a record -267.05dB FoM.

This session showcases enabling circuit blocks for next-generation sub-THz transceivers. The talks span key front-end functions such as attenuation, low-noise amplification, frequency generation, and phase shifter, targeting wideband operation and robust performance across process, voltage, and temperature.

Emerging AI workloads demand an exponential increase in XPU and switch scale-up interconnect bandwidth, alongside high-density die-to-die interfaces. This session explores novel Co-Packaged Optics (CPO) link architectures designed to meet these challenges. Presentations will highlight the use of Micro-Ring Modulators (MRM) and the enhancement of bandwidth through ultra-low-power coherent optics. Key technical deep-dives include UCIe-inspired clock-forwarding and the development of compact, power-efficient building blocks, featuring innovative Phase Interpolator (PI) designs.

GaN technologies continue to attract strong interest for applications demanding high power density. This session highlights recent advances in GaN device technologies spanning recess-free, near enhancement-mode high-performance InAlGaN/GaN HEMTs; a scalable GaN-on-Si process with high power density and linearity for FR3; heterogeneous integration of GaN power amplifiers using diamond interposers; and nonlinear electro-thermal models enabling accurate MMIC HPA prediction up to V-band.

The papers in the seesion present advanced CMOS VCO architectures achieving wide tuning ranges and state-of-the-art phase noise. Innovations include multi-tap inductors for flicker suppression, harmonic-phase tuning via transformer-based impedance control, balanced inverse-class-F operation, multiphase class-B coupling, and dual-mode series-resonance techniques, delivering high FoM across GHz frequencies with competitive power efficiency.

This session explores advanced integration technologies for Power Amplifiers (PAs) and Low-Noise Amplifiers (LNAs), pushing the boundaries of performance and size across a wide range of frequencies. The session begins with a 3D-RDL integration approach for a LDMOS Doherty PA module operating in the 3.4–3.8GHz band, demonstrating innovative packaging solutions for enhanced compactness. Next, the first GaN-on-Silicon (GaN/Si) Doherty PA operating above 7GHz is presented, showcasing the potential of GaN/Si technology for 5G FR3 applications. The session then transitions to mm-wave applications, featuring a 60GHz LNA and PA designed and fabricated in an advanced Gate-All-Around (GAA) CMOS process, demonstrating the capabilities of advanced CMOS logic technologies for mm-wave. Finally, the session ends with a 300GHz PA design in a 130nm SiGe technology, pushing the envelope of SiGe-based solutions for sub-THz applications.

GaN technologies continue to attract strong interest for applications demanding high power density. This session highlights recent advances in GaN device technologies spanning recess-free, near enhancement-mode high-performance InAlGaN/GaN HEMTs; a scalable GaN-on-Si process with high power density and linearity for FR3; heterogeneous integration of GaN power amplifiers using diamond interposers; and nonlinear electro-thermal models enabling accurate MMIC HPA prediction up to V-band.

The papers in the seesion present advanced CMOS VCO architectures achieving wide tuning ranges and state-of-the-art phase noise. Innovations include multi-tap inductors for flicker suppression, harmonic-phase tuning via transformer-based impedance control, balanced inverse-class-F operation, multiphase class-B coupling, and dual-mode series-resonance techniques, delivering high FoM across GHz frequencies with competitive power efficiency.

This session explores advanced integration technologies for Power Amplifiers (PAs) and Low-Noise Amplifiers (LNAs), pushing the boundaries of performance and size across a wide range of frequencies. The session begins with a 3D-RDL integration approach for a LDMOS Doherty PA module operating in the 3.4–3.8GHz band, demonstrating innovative packaging solutions for enhanced compactness. Next, the first GaN-on-Silicon (GaN/Si) Doherty PA operating above 7GHz is presented, showcasing the potential of GaN/Si technology for 5G FR3 applications. The session then transitions to mm-wave applications, featuring a 60GHz LNA and PA designed and fabricated in an advanced Gate-All-Around (GAA) CMOS process, demonstrating the capabilities of advanced CMOS logic technologies for mm-wave. Finally, the session ends with a 300GHz PA design in a 130nm SiGe technology, pushing the envelope of SiGe-based solutions for sub-THz applications.

This session presents low-power RF designs targeting sensing and communication applications. The first paper introduces a mixer-first pulsed-LO beam-steering receiver enabling PLL-free operation with scalable power-performance trade-offs. The second paper presents a multi-source RF energy-harvesting IC with event-driven 3-D maximum power point tracking and SIMO regulation. The third paper reports a wideband active true-time-delay circuit achieving fine delay control for efficient self-interference cancellation in full-duplex systems. The final paper demonstrates a miniature LEO satellite localization tag using algorithm–hardware co-design to reduce required EIRP by 10dB while achieving a highly compact integrated transmitter.

This session highlights recent advances in mm-wave front-end building blocks spanning LNAs, PAs, robust T/R interfaces, and a broadband LO generator. Building on the growing demands of broadband links and emerging applications such as satellite communications, the papers in this session emphasize robustness and reconfigurability alongside state-of-the-art performance. Topics include a blocker tolerant K-band LNA with strong Ka band TX rejection and a 12–28GHz LNA used to demonstrate an automated schematic-layout co-optimization platform that tightens the loop between design specs and physical implementation. On the transmit side, a comparison of two SiGe complementary mm-wave PAs, as well as a frequency reconfigurable dual band T/R front-end designed to maintain operation under severe load mismatch will be presented. A LO generator with oscillator-embedded artificial line is demonstrated for wideband next-generation radio.

This session presents recent advances in devices and circuits for system integration. Notable component advances include: a low-loss X-Band Switched-Capacitor Delay Element and signal repeater implemented in 45nm SOI CMOS technology; a dual-mode circular cavity filter; a high-performance RF-SOI switch fabricated on 130nm 200mm technology platform that incorporates a 65nm device; and a multi-channel transceiver featuring Built-in-Self-Test functionality enabled by integrated directional couplers. These papers represent significant progress in the field, driving enhanced system integration with optimized performance.

This session explores the latest advances in transceivers for the Internet of Things, focusing on ultra-low power consumption and architectural innovation. The session begins with a 2.4GHz, low-latency wake-up receiver featuring a high-efficiency, VCO-based digital demodulator. The discussion then moves to extreme energy constraints, introducing a battery-less, crystal-less, event-driven UWB tag architecture that consumes less than 100nW. A spectral- and energy-efficient tag for BPSK WiFi backscatter systems is then presented, integrating a novel sidelobe-rejection technique. The session concludes with a compact, highly efficient, BLE-compliant wireless transmitter optimized for the next generation of low-power wearable applications.

This session presents low-power RF designs targeting sensing and communication applications. The first paper introduces a mixer-first pulsed-LO beam-steering receiver enabling PLL-free operation with scalable power-performance trade-offs. The second paper presents a multi-source RF energy-harvesting IC with event-driven 3-D maximum power point tracking and SIMO regulation. The third paper reports a wideband active true-time-delay circuit achieving fine delay control for efficient self-interference cancellation in full-duplex systems. The final paper demonstrates a miniature LEO satellite localization tag using algorithm–hardware co-design to reduce required EIRP by 10dB while achieving a highly compact integrated transmitter.

This session highlights recent advances in mm-wave front-end building blocks spanning LNAs, PAs, robust T/R interfaces, and a broadband LO generator. Building on the growing demands of broadband links and emerging applications such as satellite communications, the papers in this session emphasize robustness and reconfigurability alongside state-of-the-art performance. Topics include a blocker tolerant K-band LNA with strong Ka band TX rejection and a 12–28GHz LNA used to demonstrate an automated schematic-layout co-optimization platform that tightens the loop between design specs and physical implementation. On the transmit side, a comparison of two SiGe complementary mm-wave PAs, as well as a frequency reconfigurable dual band T/R front-end designed to maintain operation under severe load mismatch will be presented. A LO generator with oscillator-embedded artificial line is demonstrated for wideband next-generation radio.

This session presents recent advances in devices and circuits for system integration. Notable component advances include: a low-loss X-Band Switched-Capacitor Delay Element and signal repeater implemented in 45nm SOI CMOS technology; a dual-mode circular cavity filter; a high-performance RF-SOI switch fabricated on 130nm 200mm technology platform that incorporates a 65nm device; and a multi-channel transceiver featuring Built-in-Self-Test functionality enabled by integrated directional couplers. These papers represent significant progress in the field, driving enhanced system integration with optimized performance.

This session explores the latest advances in transceivers for the Internet of Things, focusing on ultra-low power consumption and architectural innovation. The session begins with a 2.4GHz, low-latency wake-up receiver featuring a high-efficiency, VCO-based digital demodulator. The discussion then moves to extreme energy constraints, introducing a battery-less, crystal-less, event-driven UWB tag architecture that consumes less than 100nW. A spectral- and energy-efficient tag for BPSK WiFi backscatter systems is then presented, integrating a novel sidelobe-rejection technique. The session concludes with a compact, highly efficient, BLE-compliant wireless transmitter optimized for the next generation of low-power wearable applications.