An Ultra Low Noise 5-GHz Ring Oscillator-Based PLL with Over-Sampling Feedforward Phase Noise Cancellation Achieving -267.05 dB FoMN

A 5GHz ring-oscillator-based phase-locked loop (PLL) fabricated in 28nm CMOS achieves 198.5fs RMS jitter (1kHz–100MHz), –267.05dB normalized jitter-power figure of merit, and –247.05dB figure of merit. An oversampling feedforward phase noise cancellation architecture with an 8-phase passive gain-boosted sampler extends cancellation bandwidth to 40MHz while maintaining a –61.4dBc reference spur. The PLL occupies 0.41mm² and consumes 5mW from 0.9V/1.8V supplies.