An Ultra Low Noise 5-GHz Ring Oscillator-Based PLL with Over-Sampling Feedforward Phase Noise Cancellation Achieving -267.05dB FoMN

A 5 GHz ring-oscillator-based phase-locked loop (PLL) fabricated in 28 nm CMOS achieves 198.5 fs RMS jitter (1 kHz–100 MHz), -267.05 dB normalized jitter-power figure of merit, and -247.05 dB figure of merit. An oversampling feedforward phase noise cancellation architecture with an 8-phase passive gain-boosted sampler extends the cancellation bandwidth to 10× the loop bandwidth (40 MHz at a 4 MHz loop bandwidth) while maintaining a -67.7 dBc reference spur. The PLL occupies 0.41 mm² and consumes 5 mW from 0.9 V/1.8 V supplies.