A 60GHz LNA and PA Achieving 5dB NF and 35.6% Peak PAE in a Gate-All-Around (GAA) CMOS Process with Backside Power Delivery

This paper presents prototype designs for a 60GHz LNA and PA in a leading-edge logic process node featuring gate-all-around (GAA) CMOS transistors and backside power delivery (BSPD). Layout optimization for the amplifier unit cell (NDP) is described. Impact of magnetic feedback within the NDP array is also discussed and a mitigation technique is presented. The fabricated LNA achieves a peak gain of 27.3dB and minimum NF of 5dB while consuming 12.6mW. The PA achieves a peak gain of 22.8dB at 55GHz. At 57.5GHz, Psat/OP1dB/Peak PAE are 13.5dBm/8.5dBm/35.6% under a 0.9V supply and 14.7dBm/10.8dBm/35.7% under a 1V supply.