A 200-Gb/s Low-Noise TIA in 28-nm CMOS

This paper presents a 200-Gb/s low-noise transimpedance amplifier (TIA) implemented in standard 28-nm CMOS technology, addressing the escalating bandwidth demands of artificial intelligence data centers (AIDCs). The proposed TIA employs a three-stage front-end with a sophisticated inductive peaking strategy, a single-to-differential equalizer (S2D-EQ), and a linear CML output buffer for signal performance. The TIA achieves transimpedance gain of 61.6 dBΩ, an O-E bandwidth of 48 GHz, and an input-referred noise density of 11.5 pA/√Hz while consuming 116 mW (0.58 pJ/bit). The TIA supports 100-GBaud PAM-4 modulation, validating its suitability for next-generation high-density optical communication systems.