A 200Gbps 0.67pJ/bit Transceiver Front-end for silicon-photonic with group delay and nonlinear adjustment in 28nm CMOS

This work presents 28nm CMOS transceiver (TRX) circuitry for 3D integration with silicon-photonic (SiPh), incorporating micro-ring modulators (MRMs) and p-i-n photodiodes (PDs) to enable high-density co-packaged optics (CPO) and optical I/O (OIO). To meet the high-speed requirements of SiPh links, a combination of over-peaking and complex zero-continuous-time linear equalizer (CZ-CTLE) is employed to extend the bandwidth of both the transmitter (TX) and receiver (RX) electrical chips, while maintaining a flat group delay variation (GDV) within the 100Gbaud's Nyquist frequency (NF). Additionally, to mitigate the intrinsic nonlinearity of the MRM, an asymmetrically biased driver architecture is introduced to enhance the linearity of the optical transmitter (OTX). Measurement results show that the proposed TX (RX) supports 200Gbps (224Gbps) PAM4 signal transmission, achieving GDV below 2.28ps (1.47ps) within 100GBaud’s NF, along with bandwidth densities of 2.39Tbps/mm2 (4.9Tbps /mm2) and a total energy efficiency of 0.67pJ/bit.