An 8–28-GHz 16-Phase Delay Locked Loop Employing Nested Feedback Loops in 28-nm CMOS

This work presents a 16-phase delay-locked loop operating across 8 to 28 GHz in 28 nm CMOS. The proposed two-stage nested-feedback architecture enables the DLL to overcome the frequency limit set by the minimum delay of an inverter. An AC-coupled delay-unit structure is further introduced to suppress duty-cycle variation accumulated through multi-stage signal propagation. Fabricated in a 28 nm CMOS process, the proposed design achieves an output jitter of <47 fs and a phase error of <2.5° across 8–28 GHz.