A 6.2-GHz Reference-Feedthrough-Suppressed Type-I Sampling PLL with a Bottom-Plate-Sampling PD Scoring 18.2 fsrms Jitter, −258.7-dB FoM and −80.6-dBc Reference Spur

This paper presents a type-I sampling phase-locked loop (S-PLL) incorporating a bottom-plate sampling phase detector (BPS-PD). The BPS-PD eliminates the input reference to the voltage-controlled oscillator (VCO) feedthrough by clamping the sampling nodes to the constant common-mode potential, while ensuring a stable boosted phase detector gain through passive gain multiplication. Fabricated in a 28-nm CMOS process and integrated with a series-resonant VCO (SR-VCO), the S-PLL prototype achieves a state-of-the-art 18.2-fsrms jitter at an operating frequency of 6.2 GHz with a reference spur of −80.6 dBc. The jitter-power figure-of-merit reaches −258.7 dB.