A 224-GHz 5.9-dBm-Pout VCO Utilizing Deep-Triode-Induced Current Top-Clipping Technique

This paper presents a high-power second-harmonic voltage-control oscillator (VCO) utilizing the deep-triode-induced current top-clipping (DT-CTC) technique. By employing a cascode topology featuring a drain-source magnetic-coupling configuration, the core transistors are periodically driven into the deep triode region. This results in significant drain current top clipping, generating a waveform with high second-harmonic content. Unlike conventional cutoff-induced harmonic-generating methods, this approach overcomes output power and start-up bottlenecks. Furthermore, a quad-core coupled architecture with shared bias networks and power combining is implemented to further enhance output power and improve phase noise. The proposed VCO is fabricated in a 28-nm CMOS process and features a peak output power (Pout) of 5.9 dBm, an optimal phase noise of -112 dBc/Hz at a 10-MHz offset, a tuning range of 12.2% (211.4–235.7 GHz), and a peak figure of merit with a tuning range (FoMT) of -178.2 dBc/Hz.