A 2.4-GHz 168-fsrms-Jitter and –56-dBc-Reference-Spur RO-Based Cascaded Injection-Locked Clock Multiplier

This work presents a low-jitter, low-reference-spur ring oscillator (RO)-based cascaded injection-locked clock multiplier (ILCM). To enhance noise suppression bandwidth, the proposed cascaded ILCM integrates a reference quadrupler with a sub-harmonic injection-locked RO (SILRO). The reference quadrupler eliminates the need for additional duty-cycle calibration, while the narrow pulses generated by the quadrupler lock the SILRO, enabling a clock multiplication factor ranging from 16× to 32×. Additionally, a frequency-locking loop (FLL) and a phase-adjustment loop (PAL) are embedded within the SILRO to track the sub-harmonic injection frequency and compensate for phase deviations induced by the injection. Fabricated in a 65-nm CMOS process, the proposed prototype achieves a locking range from 1.6 to 3.2 GHz. At 2.4 GHz, the measured reference spur is −56 dBc, the RMS jitter is 167.6 fs, and the jitter figure-of-merit (FoMjitter) is −246 dB at 2.4 GHz.