A Calibration-Free 55-to-70 dBc H1 Rejection, 13.8 % Efficiency, 102-to-120 GHz CMOS Frequency Tripler using Phase-Alignment Technique for Harmonic Recombination

This paper presents a frequency tripler employing a phase-alignment-based harmonic recombination technique. By applying replicas of the input signal shifted by specific phase offsets, the unwanted odd harmonics are inherently canceled, while the wanted 3rd harmonic is enhanced. The circuit is realized in 22 nm FDSOI CMOS and operates from 102 to 120 GHz. Owing to the proposed technique, the design achieves a measured H1 rejection of 55 to 70 dBc over the entire operating bandwidth. As well, the circuit exhibits a peak efficiency of 13.8% and a peak output power of 8.2 dBm at 115 GHz.