405-GHz 2×2 Concurrent Transceiver Pixel Array with 7.8-GHz Bandwidth Using Series-Coupled Standing-Wave Oscillators

A 405-GHz 2×2 array of concurrent transceiver pixels integrating a 202.5-GHz frequency tripler, a push-push VCO and a subharmonic mixer, an IF LNA, and a patch antenna in an area smaller than (λ/2)² is used to demonstrate the techniques for scaling up concurrent transceiver pixel arrays while increasing the frequency injection locking range. The array fabricated in 22-nm FDSOI CMOS employs an injection-locked H-shaped standing-wave oscillator with a series-type current mode coupling for pixel synchronization that enables wideband locking, a 90° feed to the pixel array without mutual interference and antenna-orientation misalignment. The array exhibits a locking range of 7.8 GHz, a peak EIRP of −3.3 dBm, and a minimum DSB noise figure (NF) of 33.2 dB at 221.2-mW DC power consumption. The EIRP is the highest, NF is the lowest and the locking range is the widest (8.7×) among that for concurrent transceiver pixel arrays.