A 25.4fs Jitter Fractional-N Digital PLL with an LC-Based Power-Gated Oscillator and Series-Resonance DCO

This work presents a 10-to-12-GHz digital PLL employing a compact series-resonance oscillator to minimize out-of-band phase noise and an LC-based power-gated oscillator to suppress in-band noise and fractional spurs. Implemented in a 55-nm BiCMOS process, the PLL achieves RMS jitter of 14.9fs and 25.4fs at 11GHz integer-N and near-integer fractional-N modes, respectively, while consuming 310mW.