A 0.036 mm2, 145 GHz CMOS Power Amplifier with 7.4% PAE1dB and 4.2 dBm OP1dB for Large Arrays

We present 145 GHz power amplifiers (PAs) in 22-nm FD-SOI technology with state-of-the-art low DC power consumption and small die area. Two distinct linearization architectures are demonstrated: a PA using an adaptive back-gate voltage biasing network (ABN-PA), and a PA using diode-based linearization (DBL-PA). Both PAs use a balun output combiner. The ABN-PA achieves 12% peak power-added efficiency (PAE), 7.4% PAE1dB, 7.8 dBm Psat, and 24 dB small-signal gain using a 0.8 V supply. The core area, including supply bypass capacitors and ground wall surrounding transformers and baluns, is only 0.036 mm2. To facilitate integration into dense large-scale arrays, the PA does not require areas of exclusion to metal density rules. To our knowledge, the PAs achieve the smallest die area, DC power consumption and highest PAE1dB among reported D-band CMOS PAs.