This session focuses on advances in mm-wave and RF digital transmitter and power amplification (PA) technologies, showcasing innovative designs across various CMOS nodes. The papers enhance system-level performance and integration for modern communication systems. The first paper introduces a mm-wave transmitter using a digital-to-phase converter (DPC) in 28nm CMOS. The second presents a mm-wave digital Cartesian transmitter with impedance-compensated RFDACs in 40nm CMOS. The third explores an RF digital PA with dynamic range pulse modulation in 22nm FD-SOI. The fourth introduces a UWB all-digital transmitter with hybrid FIR filtering in 28nm CMOS. The final paper presents a bits-to-RF digital transmitter with time-interleaved multi-subharmonic-switching DPAs in 65nm CMOS.

Low Earth Orbit (LEO) satellites are unlocking new possibilities for high-speed communication systems, enabling commercial, multi-user, non-terrestrial networks. Phased arrays operating up to the mm-wave range, with high power efficiency and circuit reutilization, form the foundation of these emerging systems, ensuring both extended range and high network capacity. Advances in antenna interface flexibility, including support for various polarizations, further enhance performance. This session features four papers showcasing the latest developments in circuits, transceivers, and antenna integration solutions for large arrays.

This session presents mm-wave advances in transceivers, filtering, and heterogeneous integration. Advances include mm-wave frequency N path filtering using phase shifting in the signal path, a transceiver overcoming leakage and flicker noise for short range radar, heterogeneous integration of InP and CMOS for high linearity amplification and support circuits, and D-band radio-on-glass utilizing glass interposer for increased performance.

This session presents five high performance power amplifiers and front-end modules. The first three papers demonstrate the latest developments in GaAs power amplifiers and FEMs for the next generation 6G applications. The next two papers focus on the innovation of power amplifiers using FD-SOI technology for WiFi 6 and 5G FR-2.

This session presents recent advances in voltage-controlled oscillator (VCO) design, covering innovations across sub-THz, mm-wave, and microwave frequency bands. The first paper introduces a 60GHz coupled standing-wave-oscillator LO distribution network, enabling a 240GHz 2D phased array with area efficiency and robust performance. The second paper discusses a compact 190GHz push-push Colpitts VCO in 130nm BiCMOS, demonstrating high DC-to-RF efficiency and substantial output power. The third paper explores an image-reused phase-tuning quadrature VCO (QVCO), achieving a high figure-of-merit (FoM) through an innovative tuning technique at mm-wave frequencies. Finally, a 13.8–16.2GHz series-tank-assisted transformer-based oscillator is presented, offering excellent supply pushing characteristics and a competitive phase noise profile. These contributions highlight key innovations in VCO design across a wide range of frequencies, supporting advances in next-generation communication, radar, and sensing applications.

This session explores key mm-wave building blocks and components. The first paper presents a 28–40GHz phase shifter in 65nm CMOS, achieving less than 0.4° RMS phase error, 0.31dB RMS gain error, and a 31.5dB gain tuning range. The second paper introduces a V-band FMCW transmitter featuring an impedance-invariant voltage gain amplifier phase shifter, also in 65nm CMOS. The third paper showcases a 25–32GHz frequency doubler with up to 32% efficiency and >39dBc harmonic rejection, while the fourth paper reports a compact 24–31GHz complex impedance sensor — both implemented in 22nm FD-SOI. The session concludes with a C–X-band Wilkinson power divider/combiner utilizing a folded two-section mechanism in 65nm bulk CMOS.

This session demonstrates frequency generation in advanced FinFET CMOS and SiGe BiCMOS technologies. The first two papers present fractional-N PLLs from 13.5GHz to 23GHz in 5nm and 8nm FinFET technologies respectively. The third paper presents a distributed power-combining frequency doubler for H-band frequencies in SiGe BiCMOS. The session concludes with a circuit-under-inductor demonstration for VCOs and PAs in 6nm and 16nm technologies respectively.

The mm-wave frontier continues to advance across mainstream Si and III-V-based circuits, achieving excellent performance with enhanced functionality. This session presents a diverse set of circuits and front-ends that push the boundaries of bi-directionality, bandwidth, linearity, and sensitivity. The first paper introduces a GaAs pHEMT low-noise amplifier (LNA) with a sub-3dB noise figure (NF) and wideband operation. The second paper features a 28nm CMOS dual-band LNA designed for 5G applications, offering low power consumption and NF. Next, a 40nm CMOS V-band wideband absorptive receiver with enhanced out-of-band linearity for 5G is presented. The session concludes with a 65nm CMOS bi-directional beamforming front-end, leveraging distributed impedance reshaping.

This session will cover the latest developments on high-speed ADCs, introducing time-interleaving, mismatch calibration and spur mitigation techniques. Machine learning circuits are also discussed for ADC calibration. Finally, the session closes on an ADC integrating mixed-signal multiplication stage for beamforming applications.

This session presents five papers on transmitters operating beyond 100GHz. The first paper introduces a direct-digital transmitter in the D-band using RF-DACs for RF-domain modulation. The second and third papers explore an oversampling four-channel digital-to-phase transmitter and a reconfigurable quadrature second-harmonic modulator in the D-band. The fourth paper presents a 200GHz doubler-last phased array transmitter in SiGe technology. Finally, the session concludes with an amplifier-last transmitter operating from 270 to 300GHz in a 130nm SiGe BiCMOS process.

In this session, RF/mm-wave low-noise amplifiers (LNAs) and front-end modules (FEMs) are presented. Different design techniques to achieve high circuit performance in terms of wide bandwidth, low noise, high output power, and superior PAE are proposed. For the first paper, a 23–40GHz LNA with a dual-path noise-cancelling technique is demonstrated. The second paper is an LNA operating at V and E frequency bands with a three-line coupler to provide wide-band noise and power matching. The third paper presents a sub-10GHz RF front-end module composed of a digital PA with a 4-way balanced power combining network and an LNA with a dual-resonant input matching approach. For the fourth paper, a wideband bidirectional switchless PA-LNA with 8-shaped transformers for W frequency bands is proposed. The final paper is a 24–30GHz GaN-on-SiC FEM with a 37.1dBm output power and 34.4% PAE.

This session showcases the latest advances in energy-efficient and high-linearity IoT RFIC design. The first paper presents a backscatter communication IC achieving high modulation order and strong sideband suppression. The session then features a next-generation 5G wake-up receiver leveraging multi-carrier OOK modulation for low-power and high-sensitivity IoT applications, followed by a harmonic-suppressing low-power receiver design. A novel scaling-friendly time-domain technique is introduced to enhance the linearity of an energy-efficient receiver. Finally, a fully integrated galvanic isolator achieves low power for asynchronous full-duplex communication.

This technical session explores the evolving demands of next-generation communication, radar, imaging, and SATCOM applications. The session will address the challenges for achieving high output power, efficiency, linearity, bandwidth, and robust performance. The first paper presents a 10–40GHz stacked push-pull PA that enhances both bandwidth and linearity through the harmonic superposition of drain-source waveforms. The second paper focuses on a V-band PA featuring a dual-mode slotline-based series-parallel combiner. The third paper introduces a D-band Doherty PA incorporating a Guanella transformer and adaptive bias. The fourth paper presents a process robust K-band balanced PA with a current-mode adaptive bias circuit. The final paper demonstrates a 5G phased-array TX with load compensating Doherty PA.

This session consists of five papers on advanced techniques for high-performance oscillators operating at RF frequencies. The first paper introduces an inverse-class-F VCO utilizing a distributed dual-mode resonator (DMR) instead of a transformer-based tank, enhancing high-Q performance at both fundamental and second harmonic frequencies while suppressing noise conversion and minimizing detrimental third harmonic components. The second paper introduces a quad-core quad-mode VCO utilizing a pure magnetic-coupling technique and a fully symmetrical topology, featuring a centrosymmetric transformer with four coupled inductors and an embedded switched inductor to enable quad-mode operation without frequency tuning range degradation. The third paper presents a series resonance oscillator with bidirectional inductive-mode pulling, enabling ultra-low phase noise and wide tuning range by optimizing mode-switching connections, introducing a balanced-slope NMOS inverter for ripple minimization, and ensuring reliable frequency expansion without added parasitic effects. The fourth paper introduces a coupling-canceling common-mode resonance expansion technique using a tail 8-shaped inductor and staggered tap inductors to enhance wideband common-mode impedance, effectively reducing flicker phase noise without requiring manual tuning. The last paper introduces a multi-tap transformer-based quad-core dual-mode VCO that leverages enhanced electromagnetic mixed-coupling and harmonic-free-like techniques to achieve wideband flicker noise suppression while employing orthogonally stacked dual-core transformers and mode switches to enable a wide frequency tuning range.

This session starts with a low-power analog-mixed-signal machine-learning classifier for wireless signals. This is followed by a fast beam-forming system and a silicon-photonic driver. Finally, a UWB SoC for next-generation ranging and a biomedical sensor are presented.

This session covers recent developments, advanced design techniques, and methodologies in high performance RF and mm-wave SiGe PAs. The first paper introduces a new design methodology for algorithmic inverse design and optimization of multi-stage power-combined mm-wave PAs. The second paper demonstrates the first silicon-based PA providing multiple watts of power at Ka-band. The next paper is a 17–30GHz SiGe common-collector common-base PA with enhanced large-signal stability for SATCOM application. The fourth paper presents an efficient Q-band balanced PA designed using a two-tone load-pull optimization technique. The last paper demonstrates a compact, reconfigurable dual-band 5/6GHz SiGe PA for Wi-Fi 6E application.

This session presents integrated systems and techniques introducing breakthroughs in energy efficiency, accuracy and sensitivity of mm-wave radars and sensors. This includes precision sub-THz near field sensors, an interference cancellation technique for FMCW radars, and an energy-efficient phase-modulated radar SoC for joint radar and communication applications.

Heterogeneous integration is one of the most interesting technology areas that is quickly finding its place in RF and mm-wave applications. This session consists of four papers describing circuits and systems implemented by integrating chips fabricated in different semiconductor technologies into one solution platform. The fifth paper describes a single source impedance thermal noise measurement technique. The session starts with the presentation of a heterogeneously integrated power amplifier module using BiCMOS and RF SOI CMOS chips. The second paper presents integration of GaN circulator with RF SOI voltage boosted clock generation IC. The next paper describes a GaN amplifier embedded in a glass substrate. The fourth paper presents the 3D-integration platform for scaled GaN-on-Si dielets with Intel 16 Si CMOS. The final paper described a formalism for determining thermal noise parameters for MOSFET transistors that requires only single source impedance measurements.

This session covers high performance PLL and frequency multiplier techniques. The first paper presents a high performance D-band double-sampling PLL with 35.1fs jitter. The second paper demonstrates a THz synthesizer using 85GHz CP-PLL and frequency quadrupler with optimal impedance matching technique. The session also includes a digital background calibration LMS technique for a robust wide-band frequency tripler. The fourth paper presents an injection locked frequency tripler with an amplitude detection method to enhance frequency tracking. Lastly, a compact W-band differential doubler is presented with high conversion gain and >36dBc fundamental rejection ratio.

The focus of this session is to introduce innovative D-band circuits and systems in the sensing and communication domains. We start with a 129–148GHz radar transceiver achieving broadband performance through the TL-MCR concept followed by a 169GHz sparse chirp-stitched radar system in 40nm CMOS with an impressive range resolution of 1mm. The third paper is a >27% tuning range sub-sampling PLL in 28nm CMOS. A novel switching mechanism for BPSK modulation for backscattering application is reported in the fourth paper. We close the session with a D-band TRX chipset with >40dB IRR and very low-loss 4-way power combiner built using a novel enhanced magnetic coupling cavity with transmission line (EMCC-TL).

High-speed circuits are essential to the efficient control and driving of upcoming photonic and quantum systems. This session features a diverse set of papers for such applications. The first paper covers a widely reconfigurable temperature-scalable cryogenic PLL. The second paper covers a low-power correlator targeting communications and compute-in-memory applications. Papers 3 and 4 cover ultra-high-speed drivers for photonic transceivers, designed in FD-SOI CMOS and SiGe BiCMOS respectively. The final paper covers a set of integrated circuits designed in GaAs as an oscilloscope front-end system.

This session presents circuit techniques for radars and phased arrays, achieving good energy and area efficiency, wider bandwidth with improved detection range and resolution. A 1TX/4RX FMCW radar chipset exploits multi-band to achieve an angular resolution of 6deg. Baseband techniques are then presented, achieving 800MHz signal bandwidth for phase array and 7.5cm resolution for PMCW with good area and energy efficiency. Finally, two radars for vital-sign detection, with multi-mode IR-UWB radar achieving detection range up to 10m, and another combined FMCW and Doppler radar work with shared building blocks, achieving small chirp frequency error of 0.04%.

In this session, the generation of D-band signals using a tripler with adaptive biasing and a regenerative frequency shifter will be presented. For interfacing transmitter and receiver elements to a single antenna, the session will include a presentation on an integrated quasi circulator, based on a coupled-line coupler with tunable termination. The session will also present a compact PA for phased arrays to enable scaling of half-wavelength spaced array elements as well as a wideband PA that provides full D-band coverage by utilizing coupled-line-based matching networks.

This session explores cutting-edge techniques for designing high-performance receiver front-ends, focusing on achieving superior sensitivity, linearity, and blocker rejection while minimizing power consumption. The presented papers delve into novel architectures and circuit techniques, including passive filtering, mixer-first topologies, active feedback, and capacitive stacking, pushing the boundaries of receiver performance across various frequency bands.