In this session five mm-wave integrated transmitters, receivers, phase arrays suitable for wireless communication and sensing are presented. The session starts with a 60GHz positive-feedback-based transmitter front-end with a maximum 22.8% PAE in 28nm bulk CMOS for inter-satellite communications. The second paper reports A Ka-band 8-element 4-Beam transmitter front-end with hybrid VGA and symmetrical transformer-based Doherty PA. The third paper describes a 32-element 25.8–30.8GHz phased-array CMOS transmitter with programable temperature compensation technique that achieves ±0.002dB/°C gain variation across -60-to-85°C. The fourth paper demonstrates a 45nm SOI 5G blocker-tolerant mm-wave MIMO receiver with up to 41dB spatial notch filtering. Final paper of the session reports a 56–65GHz FMCW radar transceiver with 7.8dB NF and 8GHz chirp-bandwidth in 65nm CMOS.

This session is dedicated to advances in Silicon and III-V technologies enabling innovative mmW IC design ultimately leveraging advanced packaging including heterogeneous integration strategies to develop next generation mmW systems. The first paper of the session will describe a wideband 5G FR2 5G FEM in 150-nm GaN on SiC technology. The second paper will then extend III-V technology capability by proposing an innovative heterogeneous integration with Silicon technology. The third paper focuses on advanced packaging by presenting a high performance glass interposer targeting D-band mmW system. The fourth paper presents advances in Silicon technologies by introducing an innovative LDMOS device in 22-nm FD SOI technology targeting Wi-Fi power amplifiers, while the fifth and final paper will complement this update on PA design by introducing an innovative wideband directional coupler design achieved in RF SOI technology.

This session provides an overview of the latest advances in RF systems for low-power sensing and 5G applications. It features a self-reconfigurable RF energy harvesting system with voltage regulation and wide power dynamic range as well as a compact RFSOI CMOS 5G phased array transceiver with outstanding TX average output power performance and RX noise figure. The session then introduces a novel RF sensing system with enhanced linearity and dynamic range for microplastic detection followed by a record harmonic-rejection-ratio frequency quadrupler for 5G applications and a time-division power and data transfer system for wirelessly powered biopotential sensing.

This session presents a variety of techniques for mm-wave and RF circuits. The papers report bi-directional front-ends and integrated TRSW-LNA-PA for 5G and SATCOM communications, along with a J-band TX/RX chipset and a variable attenuator for power detection applications.

This session presents advances in VCO performance, employing multi-mode, multi-core architectures, and Impulse Sensitivity Function (ISF) shaping. The first two papers extend frequency tuning range with multi-mode architectures. The third paper reduces phase noise in a triple-push, triple-core DCO for V-band operation. The fourth paper achieves record phase noise reduction in CMOS by combining series resonance in a multi-core architecture. Finally, the last paper demonstrates improved phase noise through ISF shaping with a multi-tank topology.

This session presents novel techniques for energy efficient performance enhancements to wireless transmitters and receivers. The first paper presents an IoT transmitter employing amplitude and phase calibration to improve harmonic rejection, followed by techniques to improve receiver blocker tolerance using novel N-path mixer-first front-end topologies. An energy-efficient polar receiver based on a phase tracking architecture capable of amplitude demodulation is then presented, followed by a phase noise canceling receiver.

In this session five papers on mm-wave power amplifiers are presented. The session starts with a 60GHz PA in FDSOI CMOS with 42.3% PAE. The second paper presents a three-way combining wideband PA to achieve high backoff efficiency without load modulation. The third paper demonstrates a 22–44GHz Doherty PA with 3:1 VSWR variation tolerance. The fourth paper presents a true power detector scheme to achieve >33dB dynamic range. The last paper demonstrates a dual-mode PA to support sub-6GHz and mm-wave for 5G FR1 and FR2, respectively.

This session presents recent advances in RF and mm-wave frequency multiplication techniques. The session starts with two papers on inductorless wideband frequency doubler and multiplier designs, followed by two injection-locking frequency tripler and multiplier designs. Lastly, we present an mm-wave frequency tripler with power combining and harmonic shaping techniques.

This session covers several innovations in the design of components for phased arrays. The first three papers present phased array receivers achieving high resolution and demonstrating accurate phase-shifter and multibeam capabilities up to the W-band. The last two papers showcase additional crucial components by presenting a high-linearity VGA and a reconfigurable front-end for 5G.

This technical session focuses on addressing the demands of next-generation high-speed communication, high-resolution radar/imaging, and sensing applications, which necessitate high-power (>15dBm) and high-efficiency power amplifiers (PAs) operating at D-band frequencies and above (>100GHz). The session will delve into the design challenges associated with achieving improved output power, efficiency, linearity, and bandwidth in high-performance silicon-based PAs, utilizing technologies such as SOI CMOS and SiGe. The first paper presents a high Pout and efficient PA operating at 130–151GHz, implemented in 22nm FD-SOI technology. It features a fully differential 8-way power combining network, enhancing Pout, and linearity. The subsequent two papers present advanced architectures and design techniques utilizing 45nm RF-SOI technology: Complex neutralization for source-gate-driven cascode PA and a cascade-stacked PA architecture. The last paper introduces a novel asymmetric slotline-based series-parallel combiner implemented in 130nm SiGe BiCMOS technology, designing upper frequency bands up to 270GHz.

In this session, you will learn about 5 different CMOS frequency synthesis solutions that cover a range of frequencies from low-GHz to sub-THz. These solutions are particularly relevant for applications such as FMCW radars and the upcoming 5G to 6G communications. The papers proposing these solutions are highly innovative and offer valuable insights.

This session will present advanced wireline and localization systems. It includes a very wide bandwidth low distortion TIA for coherent optical communications. The second paper introduces an eye-opening monitor exploiting non-uniform sampling and quantization. The third paper presents a beamforming array with true-time delay for angle of arrival estimation. The last paper demonstrates a frequency-encrypted FMCW LiDAR using an electro-optical synthesizer.

This session highlights cutting-edge developments in cryogenic circuits and modeling in both CMOS and BiCMOS processes including a multicore VCO for bandwidth extension, a noise cancelling low-noise amplifier for low power consumption, and a multi-channel waveform generator for quantum applications. An experimental study on radiation effects on a Ka Band PLL showing phase noise effects is presented.

In this session, advanced digital PA and TX systems for 5G-NR, Wifi-7, and IoT applications are developed. Firstly, a 16nm FinFET watt-level WiFi-7 all-digital polar TX using switched capacitor digital PA is introduced. Secondly, a SAW-less RF transmitter based on N-path switched-capacitor modulator is proposed for 5G-NR CIM3 cancellation. Thirdly, a high power quadrature complex domain Doherty PA using switched constant-current and symmetrical transformer is developed for deep PBO efficiency enhancement. Fourthly, a 5G FR2 n260/n259 phased-array transmitter front-end IC in 28nm CMOS FD-SOI is discussed. Finally, a sub-2.4GHz transceiver with reused matching network and duty-cycle controlled Class-E PA for medical band is proposed.

This session will showcase cutting-edge innovations in silicon technology for wireless applications in D-band and beyond: system-in-package for 112.64Gb/s channel aggregation; 210–250GHz with integrated bow-tie antenna sliding-IF transceivers, dual ultra-wideband receivers, and scalable 128-channel phased arrays for dual-polarization MIMO communications are among the highlights.

This session covers PA developments in 2–40GHz range for SATCOM and other applications in CMOS, SiGe and GaN. The first paper presents a Q-band PA utilizing edge coupled-line impedance inverting balun. The next two papers cover Ku-band PAs in CMOS and SiGe with transformer area reduction techniques. The fourth paper presents an analog predistortion linearizer for a K-Band PA. The final paper demonstrates a wideband 2–18GHz GaN reconfigurable nonuniform distributed PA.

With the emerging RF applications of 5G and beyond 5G (B5G), it is desired to enable silicon-based RF front-end circuits for low-cost and high-level integration. In this session, RF front-end circuits including low-noise amplifiers and mixers in CMOS and SOI technologies are presented. The design techniques for wideband or multi-band operations are discussed and demonstrated, as well as the performance enhancement in terms of DC power reduction and noise minimization.

This session presents the latest development in D-band and THz transmitters. The first two papers present THz transmitters. The next three papers present D/F-Band transmitters all in CMOS technology with competitive data rates.

This session explores innovative circuit techniques and system applications at mm-wave and higher frequencies. The first paper discusses circuit techniques aimed at achieving wide-band performance in FMCW radars. The second paper outlines a circuit technique that achieves outstanding on/off modulation ratio in a 200GHz radar transmitter. The subsequent paper describes a radiometer that achieves the highest-frequency radiometer in an integrated silicon-based solution at 280GHz. The session concludes with a DAC-based cancellation scheme to attenuate spillover in radars utilized in automotive applications.

This session presents circuit building blocks operating in the 100–200GHz frequency range. The first paper proposes a high output power, energy-efficient Gilbert-cell-based frequency doubler with 25% duty cycle technique using 55nm BiCMOS. The second paper presents a 120GHz passive subharmonic mixer with multiphase LO distribution in 28nm CMOS. The third paper proposes a wideband 200GHz LNA which leverages the use of an active balun input stage in 16nm FinFET. The session ends with a D-band bidirectional common-gate amplifier with current-reuse technique in 45nm RFSOI.