array(3) {
  ["Sunday (4th)"]=>
  array(1) {
    ["19:30 - 9:30"]=>
    array(1) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(3) "100"
        ["title"]=>
        string(17) "Interactive Forum"
        ["date"]=>
        string(19) "Sunday, 4 June 2017"
        ["chair"]=>
        string(13) "Waleed Khalil"
        ["chair2"]=>
        string(16) "Jennifer Kitchen"
        ["chair_org"]=>
        string(16) "Ohio State Univ."
        ["chair_org2"]=>
        string(19) "Arizona State Univ."
        ["sessionId"]=>
        string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(0) ""
        ["child_sessions"]=>
        array(15) {
          ["100-1"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(90) "A Wideband Receiver With +32.5dBm Effective OB-IIP3 Using IM3 Cancellation in the Baseband"
            ["authors"]=>
            string(39) "Yudong Zhang, Jianxun Zhu, Peter Kinget"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(541) "An IM3 product cancellation technique is proposed in this work. This idea is implemented by a 65nm CMOS 0.5-2.5GHz FTNC receiver with a wideband auxiliary path which offers wideband interferer awareness and IM3 cancellation. It achieves 8.8MHz BB BW, 40dB gain, 3.3dB NF, +5dBm OB-IIP3 and ?6.5dBm OB-B1dB w/o IM3 cancellation with 36mW at 1.2V. After IM3 cancellation, the equivalent OB-IIP3 is up to +32.5dBm with an extra
34mW for two-tone interferers. For two ?15dBm modulated interferers 18.8dB cancellation is demonstrated over 10MHz."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-1"
            ["presenter"]=>
            string(12) "Yudong Zhang"
            ["presenter_org"]=>
            string(14) "Columbia Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-2"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(116) "Envelope Time-Domain Characterizations to Asses In-Band Linearity Performances of Pre-Matched MASMOS Power Amplifier"
            ["authors"]=>
            string(118) "Frédérique Simbélie, Sylvain Laurent, Pierre Medrel, Yann Creveuil, Myrianne Regis, Michel Prigent, Raymond Quéré"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(826) "This paper reports on an innovative in-band linearity performances characterization dedicated to nonlinear RF DUT (here pre-matched MASMOS® power amplifier). It consists of a generic multi-tones test signal that emulates the statistical properties of the applicative signal and allows signal and intermodulation output component separation for in-band C/I (signal to intermodulation power ratio) calculation. Two types of tests are successively discussed. The first one is a standard VSA-based measurement performed with a 16-QAM modulated signal. Secondly, a specific multi-tones signal is presented and compared with the reference VSA measurement. It is shown that the proposed generic stimulus can be used to evaluate, in specific conditions, the in-band interferences that degrade the EVM in the case of a nonlinear link."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-2"
            ["presenter"]=>
            string(22) "Frédérique Simbélie"
            ["presenter_org"]=>
            string(33) "Xlim - CNRS- Unversite De Liroges"
            ["presenter_country"]=>
            string(6) "France"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-3"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(89) "Improving the Linearity of Wideband Receiver Systems by Component IM3 Phasor Manipulation"
            ["authors"]=>
            string(104) "Gabor Varga, Fabian Speicher, Arun Ashok, Iyappan Subbiah, Moritz Schrey, Ralf Wunderlich, Stefan Heinen"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(670) "A linearization improvement technique for receiver systems is presented and verified on a 130nm CMOS high-IF upconverter with 470-790MHz input and 2.4-2.6GHz output frequency range, enabling WLAN and LTE transceivers to be used as TV White Space Devices. The upconverter reaches a stable IIP3 of 15dBm, NF of 8dB and Gain of 7dB. A linearized LNA and mixer are used as a composite architecture to combine low NF with, even though,highIIP3.Insteadoffurthermaximizingthelinearity of the components, the overall performance is optimized on thesystemlevelbymanipulationandcooperativeexploitation of the remaining third order intermodulation products of the building blocks."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-3"
            ["presenter"]=>
            string(13) "Stefan Heinen"
            ["presenter_org"]=>
            string(17) "RWTH Aachen Univ."
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-4"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(104) "A Fully-Integrated SOI CMOS Complex-Impedance Detector forMatching Network Tuning in LTE Power Amplifier"
            ["authors"]=>
            string(78) "Dominique Nicolas, Ayssar Serhan, Alexandre Giry, Thierry Parra, Éric Mercier"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(500) "This paper describes a wide dynamic-range and accurate complex-impedance detector for adaptive power amplifier load tuning systems. The detector IC, fabricated in a 130 nm SOI technology, consumes 7 mA under 2.5 V supply voltage. It can handle LTE signals with an input power from 0 dBm  up to 40 dBm  thanks to its variable attenuator system. System level measurements show that the detector has a very good accuracy in sensing the mismatched load impedance value in the VSWR region from 2:1 to 6:1."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-4"
            ["presenter"]=>
            string(13) "Ayssar Serhan"
            ["presenter_org"]=>
            string(16) "CEA-LETI Minatec"
            ["presenter_country"]=>
            string(6) "France"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-5"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(98) "V-Band Flip-Chip pHEMT Balanced Power Amplifier With CPWG-MS-CPWG Topology and CPWG Lange Couplers"
            ["authors"]=>
            string(72) "Wei-Ling Chang, Jen-Yi Su, Chinchun Meng, Chia-Hung Chang, Guo-Wei Huang"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(781) "A V-band balanced two-stage power amplifier MMICs with Lange couplers is demonstrated using 0.15 μm GaAs pHEMT technology in this paper. A CPWG-MS-CPWG topology with via holes at the transistors as the transition between coplanar waveguide with backside ground (CPWG) and microstrip (MS) is employed for the two-stage amplifier. CPWG is applied to realize the flip-chip transition interface for both input and output ports of the amplifier and inter-stage MS matching has the advantage of small size. The structure parameters of the CPWG Lange coupler and matching network are designed and optimized for power combining. Finally, a 60-GHz balanced two-stage power amplifier using a CPWG-MS-CPWG structure delivers the small signal gain of 18 dB, OP1dB of 12dBm and Psat of 15 dBm."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-5"
            ["presenter"]=>
            string(14) "Wei-Ling Chang"
            ["presenter_org"]=>
            string(25) "National Chiao Tung Univ."
            ["presenter_country"]=>
            string(6) "Taiwan"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-6"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "6"
            ["paper_title"]=>
            string(131) "Multi-Standard 5 Gbps to 28.2 Gbps Adaptive, Single Voltage SerDes Transceiver With Analog FIR and 2-tap Unrolled DFE in 28 nm CMOS"
            ["authors"]=>
            string(179) "Mohammad Mahani, Rod Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, Peter Graumann, Hans Ransijn, Tomas Dusatko, Stanley Ho, Phillip Snyder, Jomy Joy, Suresh Nalluri, Tony Zortea"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(479) "A low-power multi-standard transceiver in CMOS
28 nm is presented. The transceiver can be configured to cover the
range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver
use a supply of 0.92 V. Transmitter uses a 3-tap FIR and receiver
uses a 3-tap analog FIR and 2-tap unrolled DFE. The entire
transceiver uses single level 0.92 V power supply with an analog
power consumption of 242.3 mW at 28.2 Gbps. Total area of the
transceiver (including the CSU) is 0.88 mm2."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-6"
            ["presenter"]=>
            string(15) "Mohammad Mahani"
            ["presenter_org"]=>
            string(15) "Microsemi Corp."
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-7"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "7"
            ["paper_title"]=>
            string(100) "A Harmonic-Selective Wireless Full-Band-Capture Receiver With Digital Harmonic Rejection Calibration"
            ["authors"]=>
            string(35) "Hao Wu, David Murphy, Hooman Darabi"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(489) "A 30mW Full-Band-Capture receiver based on harmonic selection is presented. The prototype receiver employs a 32-phase non-overlapping LO, and is capable of simultaneously receiving multiple wireless signals arbitrarily located between 600MHz and 3GHz. The receiver achieves 2.4 to 5dB NF and tolerates more than –10dBm out-of-band blockers. A digital harmonic rejection calibration is also proposed to overcome phase and amplitude mismatches in the 32-phase LO and down-conversion paths."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-7"
            ["presenter"]=>
            string(6) "Hao Wu"
            ["presenter_org"]=>
            string(14) "Broadcom Corp."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-8"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "8"
            ["paper_title"]=>
            string(69) "A 40GHz PLL With -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter"
            ["authors"]=>
            string(62) "Ying Chen, Louis Praamsma, Nikola Ivanisevic, Domine Leenaerts"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(291) "This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-µm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise "
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-8"
            ["presenter"]=>
            string(9) "Ying Chen"
            ["presenter_org"]=>
            string(18) "NXP Semiconductors"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-9"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(1) "9"
            ["paper_title"]=>
            string(85) "A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS"
            ["authors"]=>
            string(28) "Yang Zhang, Patrick Reynaert"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(767) "This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout are optimized for high linearity while maintaining high gain and output power. A capacitance neutralized differential pair with source degeneration inductor for linearity enhancement is discussed. The inductive degeneration technique greatly increases the optimal load impedance, which enables a low loss parallel power combining. The complete PA achieves a measured saturated output power of 18.1dBm with 41.5% power-added efficiency (PAE). With 6 Gb/s QAM-64 signals, the proposed PA achieves an average output power of 8.4 dBm and 8.8% PAE, with -25 dBc EVM. All measurements are performed with a fixed bias condition."
            ["sessionId"]=>
            string(38) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-9"
            ["presenter"]=>
            string(10) "Yang Zhang"
            ["presenter_org"]=>
            string(9) "KU Leuven"
            ["presenter_country"]=>
            string(7) "Belgium"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-10"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "10"
            ["paper_title"]=>
            string(70) "An Analysis of Phase Noise Requirements for Ultra-Low-Power FSK Radios"
            ["authors"]=>
            string(40) "Xing Chen, Hun-Seok Kim, David Wentzloff"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(903) "This paper presents an analysis of the influence of phase noise (PN) on FSK radios and derives the PN requirement for a low power FSK link based on BER performance. A simple noise model is built, including phase noise and white noise from the AWGN channel, to analyze its influence on the BER of FSK RX. It shows that to achieve a 10-4 BER, the minimum PN requirement is much relaxed than current synthesizer designs. The trade-off between PN, data rate, and frequency deviation of the FSK modulation is also studied, showing how bandwidth can be traded for relaxed PN while maintaining the same spectral efficiency (bits/Hz). This result implies we could migrate from LC-VCOs to ROs with a simple PLL for wireless communication using FSK and significantly reduce power. A chip was fabricated to test the accuracy of the model, showing agreement among theoretical analysis, simulations and measurements."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-10"
            ["presenter"]=>
            string(9) "Xing Chen"
            ["presenter_org"]=>
            string(17) "Univ. of Michigan"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-11"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "11"
            ["paper_title"]=>
            string(72) "A Ka-Band 4-ch Bi-Directional CMOS T/R Chipset for 5G Beamforming System"
            ["authors"]=>
            string(55) "JangHoon Han, JinHyun Kim, JeongSoo Park, JeongGeun Kim"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(571) "This paper presents a Ka-band 4-ch bi-directional T/R chipset in 65 nm CMOS technology for 5G beamforming system. It is proposed to enable the bi-directional operation with the moderate gain, dual polarization mode. Each channel consists of a bi-directional gain block, a 5-bit step attenuator, a 5-bit phase shifter. The phase and attenuation coverage is 348° with the LSB of 11.25°, and 31 dB with the LSB of 1 dB, respectively. The reference state gain is > 13 dB in Tx mode and > 6 dB in Rx mode in each channel at 28 GHz including the 4-way power divider/combiner."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-11"
            ["presenter"]=>
            string(12) "JangHoon Han"
            ["presenter_org"]=>
            string(15) "Kwangwoon Univ."
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-12"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "12"
            ["paper_title"]=>
            string(112) "A 32 GHz 20 dBm-Psat Transformer-Based Doherty Power Amplifier for Multi-Gb/s 5G Applications in 28 nm Bulk CMOS"
            ["authors"]=>
            string(40) "Paramartha Indirayanti, Patrick Reynaert"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(664) "This paper presents a 32 GHz transformer-based Doherty power amplifier (PA) in a 28 nm bulk CMOS process. There are two techniques proposed: linearization by means of AM-PM and AM-AM compensation of the class AB and the class C amplifiers; and parallel-series-parallel power power combiner, wherein a current-mode parallel combiner complements the Doherty’s voltage-mode series combiner to boost the output power. A saturated output power (PSAT ) of 19.8 dBm and an OP1dB of 16 dBm are accomplished from 1V supply while supporting 15 Gb/s 64-QAM amplification at 11.7 dBm average output power. The chip achieves 21% PAE at Psat and occupies 0.59 mm2 active area."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-12"
            ["presenter"]=>
            string(22) "Paramartha Indirayanti"
            ["presenter_org"]=>
            string(23) "Katholieke Univ. Leuven"
            ["presenter_country"]=>
            string(7) "Belgium"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-13"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "13"
            ["paper_title"]=>
            string(103) "A 10-40 GHz Frequency Quadrupler Source With Switchable Bandpass Filters and >30 dBc Harmonic Rejection"
            ["authors"]=>
            string(39) "Hyunchul Chung, Qian Ma, Gabriel Rebeiz"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(931) "This paper presents a 10>40 GHz wideband frequency quadrupler in GF8HP 0.13 μm SiGe BiCMOS process. Three bands (low-, mid-, and high-band) are implemented on-chip for wideband operation. An on-chip 4-pole switchable elliptic bandpass filter is also used to result in greatly improved harmonic rejection ratio (HRR). The measured worstcase HRR is 32-48 dBc at 11-40 GHz with an output power of +1 to -8 dBm for Pin=1 dBm (25-32 dB at 10-11 GHz). The output power and HRR remain nearly constant with Pin of 0-7 dBm. The chip is 3.96 mm2 and consumes 38 mW in low- and mid-band modes, and 62 mW for the high-band mode. To our knowledge, this wideband frequency quadrupler represents state-of-the-art performance in terms of bandwidth, HRR, Pout and power consumption. Application areas are wideband low-harmonic content sources for wideband measurement systems, high-resolution imaging systems and digital beamforming phased-arrays."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-13"
            ["presenter"]=>
            string(14) "Hyunchul Chung"
            ["presenter_org"]=>
            string(32) "Univ. of California at San Diego"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-14"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "14"
            ["paper_title"]=>
            string(95) "Joint TX and Feedback RX IQ Mismatch Compensation for Integrated Direct Conversion Transmitters"
            ["authors"]=>
            string(59) "Hunsoo Choo, Charles Sestok, Xiaoxi Zhang, Nikolaus Klemmer"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(720) "The direct conversion (DC) architecture has been adopted for wireless base-station transceivers due to its cost and area efficiency. The shortcomings of DC transceivers need to be overcome to meet their high performance requirements. In-phase (I) and quadrature phase (Q) mismatch is one of most significant impairments. This paper presents an integrated, on-line mismatch compensation system which calibrates frequency-dependent transmitter (TX) and feedback receiver (FBRX) IQ mismatches using the digital TX signal as a reference. The proposed method was fabricated in a 45nm CMOS technology. Measurements show TX ACPR of 60 dBc for 20MHz LTE low-IF signals. TX EVM of 0.8% is achieved with 20MHz zero-IF LTE signals."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-14"
            ["presenter"]=>
            string(11) "Hunsoo Choo"
            ["presenter_org"]=>
            string(23) "Texas Instruments, Inc."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
          ["100-15"]=>
          array(23) {
            ["subcom"]=>
            string(3) "100"
            ["sequence"]=>
            string(2) "15"
            ["paper_title"]=>
            string(120) "A Precision 140MHz Relaxation Oscillator in 40nm CMOS With 28ppm/ºC Frequency Stability for Automotive SoC Applications"
            ["authors"]=>
            string(45) "Dmytro Cherniak, Roberto Nonis, Fabio Padovan"
            ["location"]=>
            string(0) ""
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1930"
            ["stop"]=>
            string(3) "930"
            ["date"]=>
            string(19) "Sunday, 4 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490241618"
            ["abstract"]=>
            string(591) "The need for high-frequency, low-power, wide temperature range, precision on-chip reference clock generation makes relaxation oscillator topology an attractive solution for various automotive applications. This paper presents for the first time a 140MHz relaxation oscillator with robust-against-process-variation temperature compensation scheme. The high-frequency relaxation oscillator achieves 28 ppm/°C frequency stability over the automotive temperature range from -40 to 175°C. The circuit is fabricated in 40nm CMOS technology, occupies 0.009mm2 and consumes 294uW from 1.2V supply."
            ["sessionId"]=>
            string(39) "e1041df0-cdb9-4808-b24b-2fb73f3bf18f-15"
            ["presenter"]=>
            string(13) "Fabio Padovan"
            ["presenter_org"]=>
            string(24) "Infineon Technologies AG"
            ["presenter_country"]=>
            string(7) "Austria"
            ["start_time_num"]=>
            int(1496604600)
            ["start_h"]=>
            string(2) "19"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496568600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "30"
          }
        }
        ["start_time_num"]=>
        int(1496604600)
        ["stop_time_num"]=>
        int(1496568600)
      }
    }
  }
  ["Monday (5th)"]=>
  array(5) {
    ["8:00 - 9:40"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO1A"
        ["title"]=>
        string(46) "28GHz Phased-Array Transceivers for 5G systems"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(17) "Stefano Pellerano"
        ["chair2"]=>
        string(15) "Hossein Hashemi"
        ["chair_org"]=>
        string(11) "Intel Corp."
        ["chair_org2"]=>
        string(28) "Univ. of Southern California"
        ["sessionId"]=>
        string(38) "943726d8-2ded-43bf-83ff-d4d0bc84ed1c-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(648) "This sessions presents the latest advancements in 28GHz Phased-Array transceivers targeted for 5G systems. In the firs paper, a two-channel bi-directional phased-array chip for the construction of high-power, high-linearity base stations is presented. The second paper presents a four-element transceiver with scalar-only weighting functions and dual-vector series feed network. In the third paper, a direct-conversion transceiver with packaged 2x4 patch antenna arrays is presented. Finally, the last paper demonstrate a low-cost 32-element phased-array architecture with 8 2x2 transceiver core chips integrated on PCB with antennas and combiners."
        ["child_sessions"]=>
        array(4) {
          ["MO1A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1A"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(117) "Bi-Directional Flip-Chip 28 GHz Phased-Array Core-Chip in 45nm CMOS SOI for High-Efficiency High-Linearity 5G Systems"
            ["authors"]=>
            string(26) "Umut Kodak, Gabriel Rebeiz"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(277) "This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error "
            ["sessionId"]=>
            string(38) "943726d8-2ded-43bf-83ff-d4d0bc84ed1c-1"
            ["presenter"]=>
            string(10) "Umut Kodak"
            ["presenter_org"]=>
            string(32) "Univ. of California at San Diego"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(85) "A 28-GHz Phased-Array Transceiver with Series-Fed Dual-Vector Distributed Beamforming"
            ["authors"]=>
            string(36) "Yi-Shin Yeh, Ed Balboni, Brian Floyd"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(829) "This paper presents a 28-GHz four-element phased-array transceiver in 130-nm SiGe BiCMOS technology for 5G cellular application. The array employs scalar-only weighting functions within each front end and a global quadrature function, enabling small footprint for each element. A dual-vector series feed network also reduces size of the array. Measurements show that each receive front end achieves 8.7 to 11.5 dB gain, 4.5 to 6.9 dB noise figure, -25.4 to -18.4 dBm input 1-dB compression point, and < 0.5-dB/2.1 RMS gain/phase error at 24 to 28 GHz. Each transmit front end achieves 9.4 to 14.3 dB gain, 5.5 to 10.6 dBm output 1-dB compression point, and < 0.4-dB/4.2 RMS gain/phase error at 24 to 28 GHz. The four-element transceiver array occupies 2.9 mm2 area and consumes 1.08 W in transmit mode and 0.68 W in receive mode."
            ["sessionId"]=>
            string(38) "943726d8-2ded-43bf-83ff-d4d0bc84ed1c-2"
            ["presenter"]=>
            string(11) "Yi-Shin Yeh"
            ["presenter_org"]=>
            string(26) "North Carolina State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(94) "A 28GHz CMOS Direct Conversion Transceiver With Packaged Antenna Arrays for 5G Cellular System"
            ["authors"]=>
            string(103) "Hong Teuk Kim, Byoung Sun Park, Seung Min Oh, Seong Sik Song, Jong Moon Kim, So Hyeong Kim, Tak Su Moon"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(424) "A 28GHz CMOS direct conversion transceiver with packaged 2x4 patch antenna arrays for 5G communication. Test results show good RF performances of NF 6.7dB, max. EIRP 31.5dBm (1PA Poutsat=10.5dBm), LO integrated phase noise -37.8dBc, best Rx/Tx EVM around 2.2% (-33.15dB), and well-fitted beam control capability. In 2 Rxs for 2x2 MIMO, reconfigurable transceivers with high data rate MIMO and long range SISO were addressed."
            ["sessionId"]=>
            string(38) "943726d8-2ded-43bf-83ff-d4d0bc84ed1c-3"
            ["presenter"]=>
            string(13) "Hong Teuk Kim"
            ["presenter_org"]=>
            string(14) "LG Electronics"
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(120) "An Ultra Low-Cost 32-Element 28 GHz Phasedm EIRP and 1.0-1.6 Gbps 16-QAM Link at 300 Meters-Array Transceiver With 41 dB"
            ["authors"]=>
            string(49) "Kerim Kibaroglu, Mustafa Sayginer, Gabriel Rebeiz"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(721) "This paper presents a 32-element phased-array architecture suitable for fifth-generation (5G) communication links. A 28-32 GHz silicon core chip is designed with 4 transmit/receive elements each with 14 dB gain and 6-bit phase control, 4.6 dB measured noise figure (NF) in the RX mode and 10 dBm output 1 dB compression point (OP1dB) in the TX mode. Eight of these chips are flipped on a low-cost PCB with integrated antennas and Wilkinson combiners. The 32-element array has a measured EIRP of 41 dBm at P1dB, can scan to 20 and 50 in Eand H-planes, and comsumes 4.2 W and 6.4 W in RX and TX modes, respectively. The array is used in a 300 meter wireless link and achieves a data rate of 1.0-1.6 Gbps at 16-QAM with "
            ["sessionId"]=>
            string(38) "943726d8-2ded-43bf-83ff-d4d0bc84ed1c-4"
            ["presenter"]=>
            string(15) "Kerim Kibaroglu"
            ["presenter_org"]=>
            string(32) "Univ. of California at San Diego"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496649600)
        ["stop_time_num"]=>
        int(1496655600)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO1B"
        ["title"]=>
        string(83) "Advanced Technologies for Optical, Millimeter Wave and Radio Frequency Applications"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(17) "Freek van Straten"
        ["chair2"]=>
        string(12) "Richard Chan"
        ["chair_org"]=>
        string(7) "Ampleon"
        ["chair_org2"]=>
        string(11) "QORVO, Inc."
        ["sessionId"]=>
        string(38) "6c52a0c9-3bfd-477c-97c4-cb6aa4ea3cc3-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(277) "Advances in specific applications for sub-THz signal generation using optical sources, advanced RFCMOS with excellent leakage performance and State-of-the-art pFET switching speed, compact low-cost quad-band filter topology and broadband power detection technique are reported."
        ["child_sessions"]=>
        array(4) {
          ["MO1B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(98) "Sub-THz Source Integrated in Low-Cost Silicon Photonic Technology Targeting 40 Gb/s Wireless Links"
            ["authors"]=>
            string(97) "Elsa Lacombe, Frederic Gianesello, Cedric Durand, Guillaume Ducournau, Cyril Luxey, Daniel Gloria"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(761) "Following the race for transmitting/receiving at higher data rate, we can observe intensive development of millimeter-wave wireless systems in low-cost CMOS technology. Data rates above 10 Gb/s are now targeted in order to address the data traffic bottleneck of backhaul links for the 5G wireless network. To do so, antenna-systems operating at sub-THz frequencies show great potential, leveraging high-performance photonic technology.  This paper presents a sub-THz source based on a SiGe PIN photodiode integrated in low-cost Silicon Photonic technology. Using a laser beat-note, the photodiode delivers an output power ranging from  -20 dBm to -29 dBm between 125 and 325 GHz. Leveraging this wide operating band, data rate exceeding 40 Gb/s can be targeted."
            ["sessionId"]=>
            string(38) "6c52a0c9-3bfd-477c-97c4-cb6aa4ea3cc3-1"
            ["presenter"]=>
            string(19) "Frederic Gianesello"
            ["presenter_org"]=>
            string(18) "STMicroelectronics"
            ["presenter_country"]=>
            string(6) "France"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1B-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(63) "RF NMOS Switch With Dedicated Sinks for Reduced Leakage Current"
            ["authors"]=>
            string(98) "Mahmoud S. M. Al-Sa'di, Johan J. T. M. Donkers, Peter H. C. Magnée, Ihor Brunets, Jan W. Slotboom"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
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            string(3) "940"
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            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(549) "In this paper we introduce a method to significantly reduce the substrate leakage current in an RF NMOS switch device without degrading the device figure-of-merit (Ron×Coff), and with no increase in device complexity. This is based on modifying the structure layout, and introducing dedicated sinks. These sinks prevent the substrate’s minority carriers from reaching the source/drain regions, thereby removing it from the signal path. In addition, this approach allows independent tuning of two parameters, leakage and Ron×Coff figure-of-merit."
            ["sessionId"]=>
            string(38) "6c52a0c9-3bfd-477c-97c4-cb6aa4ea3cc3-2"
            ["presenter"]=>
            string(22) "Mahmoud S. M. Al-Sa'di"
            ["presenter_org"]=>
            string(18) "NXP Semiconductors"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
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            string(2) "00"
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            int(1496655600)
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            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(53) "RF-pFET in Fully Depleted SOI Demonstrates 420 GHz FT"
            ["authors"]=>
            string(311) "Josef Watts, Kumaran Sundaram, Kok Wai Chew, Shih Ni Ong, Steffen Lehmann, Wai Heng Chow, Lye Hock Kelvin Chan, Jerome Mazurier, Christoph Schwan, Yogadissen Andee, Thomas Feudel, Luca Pirro, Elke Erben, Edward Nowak, Elliot Smith, El Mehdi BAZIZI, Thorsten Kammler, Richard Taylor III, Bryan Rice, David Harame"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
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            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(579) "We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility."
            ["sessionId"]=>
            string(38) "6c52a0c9-3bfd-477c-97c4-cb6aa4ea3cc3-3"
            ["presenter"]=>
            string(11) "Josef Watts"
            ["presenter_org"]=>
            string(15) "GLOBALFOUNDRIES"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
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            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(124) "Validation of a Functional Principle for a Broadband Millimeter-Wave Power Detection Structure in a Recent BiCMOS Technology"
            ["authors"]=>
            string(47) "Florian Trenz, Robert Weigel, Dietmar Kissinger"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(946) "In this paper, a functional principle for a broadband thermal detector suited for a monolithical integration is shown. Two tantalum load resistors are heated by an input signal, while the temperature at a fixed distance is recorded on chip with a differential temperature sensing bridge.
An integrated differential to single-ended stage amplifies the bridges differential voltage and makes an output voltage proportional to the input power of the detector available.
The thermal resistance and capacitance between the load resistor and the sensing cell act as a low pass filter in the electrical regime.
Based on this concept, a detector chip has been designed, which has been analyzed in thermal simulations.
The realized detector has been characterized on-chip and bonded to a microwave substrate for a system performance estimation.
Its input impedance is tuned to 50 Ohms and measured matching is better than -15dB from 10MHz to 43.5GHz."
            ["sessionId"]=>
            string(38) "6c52a0c9-3bfd-477c-97c4-cb6aa4ea3cc3-4"
            ["presenter"]=>
            string(13) "Florian Trenz"
            ["presenter_org"]=>
            string(27) "Univ. of Erlangen-Nuremberg"
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496649600)
        ["stop_time_num"]=>
        int(1496655600)
      }
      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO1D"
        ["title"]=>
        string(39) "High-Performance Frequency Synthesizers"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(18) "Jeyanandh Paramesh"
        ["chair2"]=>
        string(11) "Jaber Khoja"
        ["chair_org"]=>
        string(21) "Carnegie Mellon Univ."
        ["chair_org2"]=>
        string(22) "Rockwell Collins, Inc."
        ["sessionId"]=>
        string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(315) "The session deals with high-frequency generation schemes for different applications as automotive radars, rotational spectroscopy and clock generation for digital systems. A beyond-state-of-the-art digital PLL for an LTE-A polar transmitter and an inductor-less sub-sampling fractional-N PLL will be also presented."
        ["child_sessions"]=>
        array(5) {
          ["MO1D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(66) "A 59-to-276 GHz CMOS Signal Generation for Rotational Spectroscopy"
            ["authors"]=>
            string(36) "Xiaolong Liu, Yue Chao, Howard Luong"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490760018"
            ["abstract"]=>
            string(655) "An ultra-wideband sub-THz signal generation system is proposed for rotational spectroscopy employing a magnetic-tuning varactor-less quad-band voltage-controlled oscillator (QB-VCO), a locking-range-enhanced dual-mode injection-locked frequency divider (DM-ILFD), a power-efficient injection-locked oscillator (ILO) as a driver, and sub-THz mixers with frequency multipliers for frequency extension. Implemented in a 65-nm CMOS process and consuming 54 mW, the prototype measures an ultra-wide frequency tuning range from 58.8 to 275.6 GHz with 10-MHz offset phase noise from -115.8 dBc/Hz to -89.2 dBc/Hz while occupying a core area of 0.9 mm × 0.72 mm."
            ["sessionId"]=>
            string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-1"
            ["presenter"]=>
            string(12) "Xiaolong Liu"
            ["presenter_org"]=>
            string(41) "Hong Kong Univ. of Science and Technology"
            ["presenter_country"]=>
            string(9) "Hong Kong"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(159) "A Fully Integrated 75-83 GHz FMCW Synthesizer for Automotive Radar Applications With -97 dBc/Hz Phase Noise at 1 MHz Offset and 100 GHz/mSec Maximal Chirp Rate"
            ["authors"]=>
            string(53) "Jakob Vovnoboy, Run Levinger, Nadav Mazor, Danny Elad"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490760018"
            ["abstract"]=>
            string(498) "We present a SiGe BiCMOS fully integrated 75-83 GHz FMCW synthesizer for automotive radar applications. Performance enhancements were achieved by utilizing the bulk-drain parasitic variable capacitance of P-channel transistors, embedded in a gm-boosted Colpitts VCO, for frequency control. This mechanism was incorporated in a dual path PLL, providing low loop bandwidth variation over the whole output frequency range, -97 dBc/Hz phase noise at 1 MHz offset and maximum chirp rate of 100 GHz/mSec."
            ["sessionId"]=>
            string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-2"
            ["presenter"]=>
            string(14) "Jakob Vovnoboy"
            ["presenter_org"]=>
            string(16) "ON Semiconductor"
            ["presenter_country"]=>
            string(6) "Israel"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(152) "A Subharmonically Injection-Locked PLL With 130 fs RMS Jitter at 24 GHz Using Synchronous Reference Pulse Injection From Nonlinear VCO Envelope Feedback"
            ["authors"]=>
            string(58) "Dongseok Shin, Shinwoong Park, Sanjay Raman, Kwang-Jin Koh"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490760018"
            ["abstract"]=>
            string(462) "This paper presents an 8 GHz subharmonically injection-locked PLL (SILPLL), which is cascaded with a 24 GHz quadrature injection-locked oscillator in 130 nm CMOS. The proposed SILPLL adopts an envelope-detection based injection-timing calibration for synchronous reference pulse injection to a VCO. With one of the largest frequency division ratios (N=80) reported so far, the SILPLL exhibits 124 fs and 130 fs RMS jitter at 8 GHz and 24 GHz, respectively, with "
            ["sessionId"]=>
            string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-3"
            ["presenter"]=>
            string(13) "Dongseok Shin"
            ["presenter_org"]=>
            string(46) "Virginia Polytechnic Institute and State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(114) "A Highly Reconfigurable RF-DPLL Phase Modulator for Polar Transmitters in Multi-Band/Multi-Standard Cellular RFICs"
            ["authors"]=>
            string(136) "Tobias Buckel, Thomas Mayer, Thomas Bauernfeind, Stefan Tertinek, Christian Wicpalek, Andreas Springer, Robert Weigel, Thomas Ussmueller"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490760018"
            ["abstract"]=>
            string(871) "A multirate, fractional-N RF digital phase-locked loop (DPLL) phase modulator implementation for polar transmitter supporting cellular communication standards up to 4G LTE-A is demonstrated for the first time. The RF-DPLL integrates LC-tank based digital-controlled oscillator (DCO) cores with delta-sigma noise shaping and fractional sample rate conversion to account for a broad range of frequency bands and spectral emission requirements. A two-point modulation with different sampling rates and signal scaling is applied to optimize the system for operation in narrow-band and wide-band phase modulation. DCO predistortion and DCO gain estimation is implemented to achieve sufficiently low in-band distortion. Measurement results of the RF-DPLL system as part of a polar transmitter implemented in 28-nm CMOS are shown fulfilling 3GPP specifications for LTE-A uplink."
            ["sessionId"]=>
            string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-4"
            ["presenter"]=>
            string(13) "Tobias Buckel"
            ["presenter_org"]=>
            string(40) "Danube Mobile Communications Engineering"
            ["presenter_country"]=>
            string(7) "Austria"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO1D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO1D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(82) "A Low-Noise Inductor-Less Fractional-N Sub-Sampling PLL With Multi-Ring Oscillator"
            ["authors"]=>
            string(32) "Dongyi Liao, Ruixin Wang, Fa Dai"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490760018"
            ["abstract"]=>
            string(734) "In this paper, a compact inductor-less PLL using multiple coupled rings oscillator is presented. Sub-sampling technique with robust loop switching is applied to reduce the in-band phase noise. As a result, the loop bandwidth can be widened, which suppresses the phase noise from ring oscillator as well. Fractional-N mode is implemented by utilizing the multiple phase outputs inherently generated by the ring VCO. The PLL was implemented in a 0.13um CMOS technology, consuming 19 mW from a 1.3 V power supply. The measured largest in-band fractional spur at 2.08 MHz is -42 dBc. The measured integrated jitters around 1.2GHz output in integer mode and fractional mode were 571 fs and 690 fs, respectively, achieving a FoM of -232 dB."
            ["sessionId"]=>
            string(38) "64b72f42-a85e-4cf9-96c3-06c529a320d7-5"
            ["presenter"]=>
            string(11) "Dongyi Liao"
            ["presenter_org"]=>
            string(12) "Auburn Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496649600)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496655600)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
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        }
        ["start_time_num"]=>
        int(1496649600)
        ["stop_time_num"]=>
        int(1496655600)
      }
    }
    ["10:00 - 11:40"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO2A"
        ["title"]=>
        string(36) "Radio Building Blocks for 5G Systems"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(15) "Walid Ali-Ahmad"
        ["chair2"]=>
        string(16) "Bodhisatwa Sadhu"
        ["chair_org"]=>
        string(14) "Qualcomm, Inc."
        ["chair_org2"]=>
        string(31) "IBM T.J. Watson Research Center"
        ["sessionId"]=>
        string(38) "1a36c586-0e47-443f-9e6f-df1c10b89a6b-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(621) "This session presents key building blocks for radio transceivers targeted for 5G systems. The first paper describes an 8-element, 2-stream hybrid beamforming receiver for MIMO communication operating at 25-30GHz. In the second paper, a wideband 29-to-57GHz power amplifier with AM-PM compensation for 5G phased-arrays is presented. In the last two papers, two digital beamforming solutions are described: a quad-channel, 1GS/s collaborative ADC for a four-channel MIMO receiver and a 16-element, 4-beam digital beam-former combining continuous-time band-pass delta sigma modulators with interleaved bit-stream processing."
        ["child_sessions"]=>
        array(4) {
          ["MO2A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2A"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(81) "A 25-30 GHz 8-Antenna 2-Stream Hybrid Beamforming Receiver for MIMO Communication"
            ["authors"]=>
            string(62) "Susnata Mondal, Rahul Singh, Ahmed Hussein, Jeyanandh Paramesh"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(873) "This paper presents a 65 nm CMOS 25-30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams. The receiver uses the Cartesian-Combining architecture, which is introduced for two baseband streams. Each antenna signal is complex weighted independently and combined with weighted signals from other antennas prior to downconversion. Each RF domain complex weight is realized using a pair of 5-bit digitally controlled VGA’s. The receiver achieves 34 dB conversion gain, 7.3 dB minimum noise figure, and 5 GHz of RF bandwidth while consuming only 27.5 mW power per antenna element (340 mW for the entire receiver). Two element Cartesian-combining achieves a peak-to-null ratio of 20 dB. Use of mostly active phase shifting and combining approach made the design ultra-compact with 3.86 mm2 core area for entire 8-element 2-stream receiver."
            ["sessionId"]=>
            string(38) "1a36c586-0e47-443f-9e6f-df1c10b89a6b-1"
            ["presenter"]=>
            string(14) "Susnata Mondal"
            ["presenter_org"]=>
            string(21) "Carnegie Mellon Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(100) "A 29-to-57GHz AM-PM Compensated Class-AB Power Amplifier for 5G Phased Arrays in 0.9V 28nm Bulk CMOS"
            ["authors"]=>
            string(33) "Marco Vigilante, Patrick Reynaert"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(225) "This paper presents a 29-to-57GHz (65% BW) AM-PM compensated class-AB power amplifier tailored for 5G phased arrays. Designed in 0.9V 28nm CMOS without RF thick top metal, the PA achieves a Psat=15.1dBm±1.6dB and │AM-PM│"
            ["sessionId"]=>
            string(38) "1a36c586-0e47-443f-9e6f-df1c10b89a6b-2"
            ["presenter"]=>
            string(15) "Marco Vigilante"
            ["presenter_org"]=>
            string(23) "Katholieke Univ. Leuven"
            ["presenter_country"]=>
            string(7) "Belgium"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(98) "A Quad Channel 11-bit 1 GS/s 39.56 mW Collaborative ADC Based Digital Beamforming for 5G Wireless."
            ["authors"]=>
            string(43) "Aurangozeb, Farshid Aryanfar, Masum Hossain"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(519) "A 4x11-bit 1 GS/s 39.56 mW Collaborative ADC in 65nm CMOS is presented for a 4-Ch MIMO receiver. It utilizes the correlation information between channels to perform energy efficient digitization of received signals. By utilizing 8 SAR units each with 6-bit resolution, four resolution of ADC, 11, 9,6, and 6-bit, can be achieved during runtime. This collaborative ADC performance is compared with all-11 and all-9 bit. It reduces area and power by half and 40.94% respectively with only 10% degradation of overall SNDR."
            ["sessionId"]=>
            string(38) "1a36c586-0e47-443f-9e6f-df1c10b89a6b-3"
            ["presenter"]=>
            string(10) "Aurangozeb"
            ["presenter_org"]=>
            string(16) "Univ. of Alberta"
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(99) "A 16-Element 4-Beam 1GHz-IF 100MHz-Bandwidth Interleaved Bit Stream Digital Beamformer in 40nm CMOS"
            ["authors"]=>
            string(51) "Sunmin Jang, Jaehun Jeong, Rundao Lu, Michael Flynn"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491840018"
            ["abstract"]=>
            string(884) "This paper introduces a 16 element, 1GHz IF input, digital beamformer (DBF) that generates 4 independent simultaneous beams, with 100MHz bandwidth. Although DBF has several advantages over analog beamforming, including higher accuracy and multiple beam generation, application of on-chip DBF has been limited due to high power consumption and large die area. The proposed architecture addresses these issues by combining efficient Continuous-Time Band-Pass Delta Sigma Modulators (CTBPDSMs) with Interleaved Bit-Stream Processing (IL-BSP). IL-BSP saves 80% power and 80% area compared to a conventional DSP approach. The overall 16 element array has a measured 58.5dB SNDR over a 100MHz bandwidth (10.5dB array gain). Thanks to the IL-BSP approach, the measured beam patterns are near ideal. Among state-of-the-art beamformer ICs, this prototype achieves the best power and area FoMs."
            ["sessionId"]=>
            string(38) "1a36c586-0e47-443f-9e6f-df1c10b89a6b-4"
            ["presenter"]=>
            string(11) "Sunmin Jang"
            ["presenter_org"]=>
            string(17) "Univ. of Michigan"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496656800)
        ["stop_time_num"]=>
        int(1496662800)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO2B"
        ["title"]=>
        string(88) "Modeling and Characterization for Emerging High Frequency and RF Front-end Applications "
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(13) "Tzung-Yin Lee"
        ["chair2"]=>
        string(15) "Edward Preisler"
        ["chair_org"]=>
        string(18) "Skyworks Solutions"
        ["chair_org2"]=>
        string(9) "TowerJazz"
        ["sessionId"]=>
        string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(448) "This session begins with modeling of RF switches for wireless front-end applications, followed by practical CMOS FET modeling for RF IC design, and test structure design optimization for very high-frequency characterization.  Next, modeling of SMT devices, which are integral in today’s commercial front end modules, is presented.  Finally, modeling of GaN HEMTs is discussed with an emphasis on large-signal vs. small-signal characteristics."
        ["child_sessions"]=>
        array(5) {
          ["MO2B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(123) "Accurate Modeling and Optimization of Inhomogeneous Substrate Related Losses in SPDT Switch IC Design for WLAN Applications"
            ["authors"]=>
            string(31) "Fadoua Gacim, Philippe Descamps"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(912) "this paper teaches the way to achieve an optimum substrate isolation thanks to Deep Trenches Isolation (DTI). The role of Deep Trench Isolation in substrate coupling around active blocks is analysed in link to its ability to break the conductive buried layers in the substrate. Then, an accurate modeling approach based on quasi-static approach developed for inhomogeneous substrate is investigated. The efficiency of this methodology is first demonstrated thanks to a comparison with a standard numerical method based on FEM (Finite Element Method). Then, experiments data are provided to support this theoretical analysis.  The methodology is fully integrated in a commercial design flow and offer a perfect trade-off between accuracy and run time simulation. From available test data on single device and a full SP3T, a correlation better than 0.1dB is obtained between simulation and measurement up to 8 GHz."
            ["sessionId"]=>
            string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-1"
            ["presenter"]=>
            string(12) "Fadoua Gacim"
            ["presenter_org"]=>
            string(48) "Normandie Université ENSICAEN, Unicaen, CRISMAT"
            ["presenter_country"]=>
            string(6) "France"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
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            string(2) "40"
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          array(23) {
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            string(4) "MO2B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(125) "A Simplified CMOS FET Model Using Surface Potential Equations For Inter-Modulation Simulations of Passive-Mixer-Like Circuits"
            ["authors"]=>
            string(46) "Mahmood Baraani Dastjerdi, Harish Krishnaswamy"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(987) "In many CMOS analog/RF circuits, such as passive mixers or N-path filters, the transistor operates as a switch. Switching circuits often experience source-drain reversal, and most transistor models exhibit discontinuities in second and higher-order derivatives of the drain current around zero drain-source bias. This introduces fundamental challenges in performing third-order inter-modulation distortion simulations. In this work, a method is presented to replace the factory models with equivalent surface potential models for static current in conjunction with a simple circuit to take into account second-order parasitics, namely, gate current and terminal capacitors. The modeling approach may be utilized even if device measurements are not available, is shown to be simultaneously more computationally efficient and accurate than prior approaches, and is validated through measurements from a 0.15-2.5GHz mixer-first receiver in 65nm CMOS that exhibits +34.5dBm out-of-band IIP3."
            ["sessionId"]=>
            string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-2"
            ["presenter"]=>
            string(25) "Mahmood Baraani Dastjerdi"
            ["presenter_org"]=>
            string(14) "Columbia Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(95) "Broadband Effect of Linear Tapered Transitions Between Probe Pads and GCPW Signal Lines On-Chip"
            ["authors"]=>
            string(13) "Tinus Stander"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(463) "To effect a low-reflection interconnect between GSG probe pads and on-chip GCPW, a linear taper between the signal pad and the GCPW signal line is often included. This work evaluates, both in parametric simulation and experimentation, the effect of this taper shape to the input reflection in the band 1 – 110 GHz. It is found that, although longer tapers offer some advantage below 30 GHz, the taper ultimately impedes the input reflection of the interconnect."
            ["sessionId"]=>
            string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-3"
            ["presenter"]=>
            string(13) "Tinus Stander"
            ["presenter_org"]=>
            string(22) "University of Pretoria"
            ["presenter_country"]=>
            string(12) "South Africa"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(54) "Accurate EM Simulation of SMT Components in RF Designs"
            ["authors"]=>
            string(10) "Weimin Sun"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(566) "SMD is designed into many MCM/SiP products,  but accurate EM simulation of SMD in a design has been a challenge. In fact, circuit simulation with an EM MCM model connected with vendor-provided SMT models often leads to a shift of harmonic trap notch.   Such shift may be attributed to the intrinsic inductance of an EM port.   In this paper, we focus on EM models of HFSS, present discovery of intrinsic port inductance in an HFSS model and discuss issues and techniques on how to handle lumped SMT ports in an HFSS EM model for more accurate SMD circuit simulation."
            ["sessionId"]=>
            string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-4"
            ["presenter"]=>
            string(10) "Weimin Sun"
            ["presenter_org"]=>
            string(18) "Skyworks Solutions"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2B-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2B"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(130) "Variation of Intrinsic Components From Small-Signal Model of AlGaN/GaN HEMTs in Linear and Saturation Regions After Off-State Bias"
            ["authors"]=>
            string(41) "Yue-Ming Hsin, Yi-Nan Zhong, Zhen-Wei Liu"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(675) "Current dispersion is an issue in AlGaN/GaN HEMTs. Different methods have been reported to investigate this phenomenon. This study reports an investigation of intrinsic components from small-signal model of AlGaN/GaN HEMTs right after off-state bias in linear and saturation regions in addition to drain-lag measurement. Different variations on the intrinsic components after off-state bias in linear and saturation regions were observed after switching from off-state bias. A significant current dispersion from drain-lag measurement is related to the increase in Rds and decrease in Cds extracted from small-signal model. However, less changes in Cgs and Cgd were observed."
            ["sessionId"]=>
            string(38) "72dad5c0-ecf2-4923-bb20-dc551ab06d1f-5"
            ["presenter"]=>
            string(13) "Yue-Ming Hsin"
            ["presenter_org"]=>
            string(22) "National Central Univ."
            ["presenter_country"]=>
            string(6) "Taiwan"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496656800)
        ["stop_time_num"]=>
        int(1496662800)
      }
      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO2D"
        ["title"]=>
        string(23) "mm-Wave and THz Sources"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(15) "Mohyee Mikhemar"
        ["chair2"]=>
        string(13) "Ehsan Afshari"
        ["chair_org"]=>
        string(14) "Broadcom Corp."
        ["chair_org2"]=>
        string(17) "Univ. of Michigan"
        ["sessionId"]=>
        string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(340) "Millimeter-wave and Terahertz systems have many applications in high data-rate communication, sensing, and spectroscopy. Recently there has been many works at this frequency range in silicon-based technologies. The papers in this session push the limit of mm-wave and THz sources in terms of power efficiency, phase noise, and output power."
        ["child_sessions"]=>
        array(5) {
          ["MO2D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(108) "An 8-Element Common-Mode-Coupled 106 GHz Fundamental Oscillator With -111 dBc/Hz Phase Noise at 1 MHz Offset"
            ["authors"]=>
            string(30) "Alireza Imani, Hossein Hashemi"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(648) "Phase noise reduces in a coupled array of oscillators at an ideal rate of 3N dB for 2^N oscillators. Concept of "common-mode coupling" is introduced as a robust technique in reducing phase noise in mm-wave frequencies. A 106 GHz 8-element common-mode coupled Colpitts oscillator is implemented  in a 130 nm SiGe HBT BiCMOS technology with a measured phase noise of -111 dBc/Hz at 1 MHz offset while consuming 90 mW. The core differential Colpitts oscillator uses a resonant biasing scheme to reduce phase noise. The improvement of phase noise compared to the stand-alone oscillator is 9 dB showing the effectiveness of the proposed coupling scheme."
            ["sessionId"]=>
            string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-1"
            ["presenter"]=>
            string(13) "Alireza Imani"
            ["presenter_org"]=>
            string(28) "Univ. of Southern California"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(173) "A 195 GHz Single-Transistor Fundamental VCO With 15.3% DC-to-RF Efficiency, 4.5 mW Output Power, Phase Noise FoM of -197 dBc/Hz and 1.1% Tuning Range in a 55 nm SiGe Process"
            ["authors"]=>
            string(65) "Hamid Khatibi, Somayeh Khiyabani, Andreia Cathelin, Ehsan Afshari"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(962) "A novel approach to design efficient high-output-power fundamental oscillators close to the fmax of the employed process is presented. The idea is based on shaping and optimizing the maximally efficient power gain (GME) of the circuit using a pair of internal/external feedback mechanisms. Solving a constrained optimization problem, an optimum pair of passive feedback network is designed to achieve the highest maximally efficient power gain in order to increase the output power and thence the DC-to-RF efficiency. A 195 GHz fundamental oscillator is designed in a 55nm SiGe process which achieves the highest reported DC-to-RF efficiency (15.3%) among all oscillators working above fmax/3. The oscillator generates a peak power of 6.5 dBm with the best FoM of -197 dBc/Hz measured at 100 KHz offset frequency, which is the highest among all mm-Wave oscillators. The proposed method takes into account PVT variations and modeling errors in the design process."
            ["sessionId"]=>
            string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-2"
            ["presenter"]=>
            string(13) "Ehsan Afshari"
            ["presenter_org"]=>
            string(17) "Univ. of Michigan"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(144) "Energy Efficient Distributed-Oscillators at 134 and 202GHz With Phase-Noise Optimization through Body-Bias Control in 28nm CMOS FDSOI Technology"
            ["authors"]=>
            string(63) "Raphael Guillaume, Francois Rivet, Andreia Cathelin, Yann Deval"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(678) "Two compact frequency generation topologies based on distributed oscillator architecture have been for the very first time integrated at 134GHz and 202GHz in a 10ML 28nm FDSOI CMOS technology. The efficient fundamental frequency generation enables output powers of 0.4dBm and 0.3dBm and 5.5% and 5.4% DC-to-RF efficiency respectively. The body tie of the 28nm FDSOI technology allows phase noise fine tuning through body-bias control. The measured optimum phase noises are -99.6dBc/Hz and -100.4dBc/Hz at 1MHz offset, for the two different oscillators. Robust design has been as well demonstrated, opening the way to mmW and sub-mmW SoC integration in deep submicron FDSOI CMOS."
            ["sessionId"]=>
            string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-3"
            ["presenter"]=>
            string(17) "Raphael Guillaume"
            ["presenter_org"]=>
            string(18) "STMicroelectronics"
            ["presenter_country"]=>
            string(6) "France"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(76) "A Lens-Integrated 430 GHz SiGe HBT Source With Up to -6.3 dBm Radiated Power"
            ["authors"]=>
            string(77) "Philipp Hillger, Janusz Grzyb, Stefan Malz, Bernd Heinemann, Ullrich Pfeiffer"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(784) "This paper presents a 430 GHz source implemented in a 0.13um  SiGe BiCMOS technology with fT and fmax of 300 GHz/450 GHz. The source comprises a fundamental differential Colpitts cascode oscillator at 215 GHz driving a balanced common-collector doubler that utilizes inductive second-harmonic feedback at the emitter output in order to boost the generated second-harmonic current. The doubler is co-designed with a lens-coupled on-chip circular slot antenna providing the appropriate input impedance to the doubler output. In combination with a 3-mm diameter Si-lens, the total peak radiated power is -6.7dBm at a power dissipation of 150mW. 
To the authors knowledge, the presented source shows the highest reported power for any silicon-based single-element radiator beyond 350GHz."
            ["sessionId"]=>
            string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-4"
            ["presenter"]=>
            string(15) "Philipp Hillger"
            ["presenter_org"]=>
            string(23) "University of Wuppertal"
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["MO2D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO2D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(82) "An Ultra-Wideband Harmonic Radiator With a Tuning Range of 62GHz (28.3%) at 220GHz"
            ["authors"]=>
            string(29) "Ali Mostajeran, Ehsan Afshari"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(753) "An ultra-wideband mm-wave voltage controlled oscillator (VCO) is presented. By utilizing an optimum design of the passives embedding around the core transistor in a Colpitts structure, the VCO tuning range is enhanced. The impact of DC bias on the tuning bandwidth is discussed. The generated second harmonic is efficiently extracted and radiated using a wideband slot antenna. The chip is fabricated in a 55nm BiCMOS process. A state-of-the-art tuning bandwidth of 62.1GHz (28.3%) at a center frequency of 219.6GHz is achieved. With a measured peak radiated power of -3.7dBm, a DC to radiated power efficiency of 0.52% is obtained. To the best of our knowledge, this is the largest VCO bandwidth at mm-wave frequencies compared to the state of the art."
            ["sessionId"]=>
            string(38) "3fd8d039-d434-46e4-bf04-3a9721c919a9-5"
            ["presenter"]=>
            string(14) "Ali Mostajeran"
            ["presenter_org"]=>
            string(13) "Cornell Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496656800)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496662800)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496656800)
        ["stop_time_num"]=>
        int(1496662800)
      }
    }
    ["11:45 - 12:45"]=>
    array(1) {
      [0]=>
      array(16) {
        ["subcom"]=>
        string(1) "1"
        ["title"]=>
        string(74) "5th Generation Wireless – Where is That Going and What’s in it for me?"
        ["date"]=>
        NULL
        ["chair"]=>
        string(0) ""
        ["chair2"]=>
        string(0) ""
        ["chair_org"]=>
        string(0) ""
        ["chair_org2"]=>
        string(0) ""
        ["sessionId"]=>
        string(36) "e56b6e49-e9d0-4e36-9854-8e68b9da023a"
        ["organizer"]=>
        string(43) "Oren Eliezer, Brian Floyd, Bodhisatwa Sadhu"
        ["organizer_org"]=>
        string(44) "PHAZR, North Carolina State Univ., IBM Corp."
        ["abstract"]=>
        string(446) "A panel of 5 experts from the industry and academia will debate different challenges associated with the development and deployment of 5th generation wireless systems; when and how the advancements in technologies such as massive MIMO, beamforming, phased arrays, and millimeter wave ICs will allow such systems to reach their performance and cost targets; and, of course, how will all that impact us, the community of RF engineers and end users."
        ["start_time_num"]=>
        int(1496663100)
        ["stop_time_num"]=>
        int(1496666700)
        ["color"]=>
        string(6) "4b80d6"
        ["color_id"]=>
        string(1) "9"
        ["color_name"]=>
        string(17) "Panel Discussions"
      }
    }
    ["13:30 - 15:10"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO3A"
        ["title"]=>
        string(33) "Ultra-Low Power Wake-up Receivers"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(15) "David Wentzloff"
        ["chair2"]=>
        string(14) "Arun Natarajan"
        ["chair_org"]=>
        string(17) "Univ. of Michigan"
        ["chair_org2"]=>
        string(18) "Oregon State Univ."
        ["sessionId"]=>
        string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(436) "This session presents several novel ultra-low power wake-up receivers. The first three papers are compatible with Bluetooth Low-Energy and WiFi standards by detecting either back-channel messages, or designed for the proposed 802.11 wake-up protocol. A wake-up receiver is presented with the highest reported sensitivity for a sub-1uW receiver. Finally, an RF front-end is presented leveraging a current reuse technique to reduce power."
        ["child_sessions"]=>
        array(5) {
          ["MO3A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3A"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(143) "A 2.4GHz BLE-Compliant Fully-Integrated Wakeup Receiver for Latency-Critical IoT Applications Using a 2-Dimensional Wakeup Pattern in 90nm CMOS"
            ["authors"]=>
            string(164) "Ming Ding, Peng Zhang, Chuang Lu, Yan Zhang, Stefano Traferro, Gert-Jan van Schaik, Yao-Hong Liu, Jarkko Huijts, Christian Bachmann, guido dolmans, Kathleen Philips"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(850) "This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular IoT wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired with a standard-compliant transmitter, the proposed wakeup receiver method minimizes the overhead in system power, area and complexity. The proposed 2-dimensional wakeup pattern reduces the latency of a wakeup event to below 100µs. Supplied at a battery voltage of 2V, the chip fully integrates a power management unit, a wakeup receiver with offset and noise suppression, a low power digital baseband with automatic gain control and RSSI estimation, and a crystal oscillator. With a BLE compliant signal, the chip achieves -58dBm sensitivity , and a >600s mean time without false alarm, consuming 195µA."
            ["sessionId"]=>
            string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-1"
            ["presenter"]=>
            string(9) "Ming Ding"
            ["presenter_org"]=>
            string(12) "Holst Centre"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(103) "95μW 802.11g/n Compliant Fully-Integrated Wake-Up Receiver With -72dBm Sensitivity in 14nm FinFET CMOS"
            ["authors"]=>
            string(116) "Erkan Alpman, Ahmad Khairi, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey Foerster, Ashoke Ravi, Stefano Pellerano"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
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            string(1) "0"
            ["start"]=>
            string(4) "1330"
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            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(331) "A 2.4GHz fully-integrated Wi-Fi compliant wake-up receiver in 14nm FinFET technology is presented. The receiver achieves -72dBm sensitivity and +20dBr adjacent channel interference rejection for 62.5kbps at 10-3 BER while consuming 95μW. The OOK-modulated wake-up packet can be transmitted using any legacy OFDM Wi-Fi transmitter."
            ["sessionId"]=>
            string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-2"
            ["presenter"]=>
            string(12) "Erkan Alpman"
            ["presenter_org"]=>
            string(11) "Intel Corp."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
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            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(83) "A 335µW -72dBm Receiver for FSK Back-Channel Embedded in 5.8GHz Wi-Fi OFDM packets"
            ["authors"]=>
            string(39) "Jaeho Im, Hun-Seok Kim, David Wentzloff"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(636) "An ULP back-channel receiver is presented that demodulates binary a FSK back-channel signal embedded in 5.8GHz IEEE 802.11a Wi-Fi OFDM packets. The architecture of the back-channel receiver employs a two-step down-conversion where the first mixing stage downconverts using the 3rd harmonic of the LO for power efficiency. The LP-65nm CMOS receiver consumes 335µW with a sensitivity of -72dBm at a BER of 〖10〗^(-3) and data-rate of 31.25kb/s. The radio uses a balun and a 250kHz reference crystal as external components. The receiver uses a 1V supply voltage for analog blocks, and 0.85V for digital blocks including the LO and FLL."
            ["sessionId"]=>
            string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-3"
            ["presenter"]=>
            string(8) "Jaeho Im"
            ["presenter_org"]=>
            string(17) "Univ. of Michigan"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(113) "A 365nW -61.5dBm Sensitivity, 1.875cm^2 2.4GHz Wake-up Receiver With Rectifier-Antenna Co-Design for Passive Gain"
            ["authors"]=>
            string(82) "Kamala Raghavan Sadagopan, Jian Kang, Sanket Jain, Yogesh Ramadass, Arun Natarajan"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(607) "A 2.4GHz 365nW wake-up receiver (WuRX)
with RF envelope detection using rectifier-antenna co-design
for passive voltage gain and RF filtering is presented. The RF
frequency-tunable WuRX uses a programmable 32-bit OOK
wake-up signature, achieving sensitivity of -61.5dBm for
2.5kb/s without any off-chip matching components between
IC and antenna. RF filtering in the high-Q rectifier-antenna
interface results in 10^-3 BER even with interferer-to-carrier
ratio of 19.1dB for CW blocker at 3MHz offset. The
65-nm CMOS WuRX IC occupies 1.1mm^2, while the WuRX
(including antenna) occupies 1.875cm^2."
            ["sessionId"]=>
            string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-4"
            ["presenter"]=>
            string(25) "Kamala Raghavan Sadagopan"
            ["presenter_org"]=>
            string(18) "Oregon State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3A-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3A"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(102) "A 64 uW, 23 dB Gain, 8 dB NF, 2.4 GHz RF Front-end for Ultra-Low Power Internet-of-Things Transceivers"
            ["authors"]=>
            string(74) "Anjana Dissanayake, Hyun-Gi Seok, Oh-Yong Jung, Sok-Kyun Han, Sang-Gug Lee"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(733) "An ultra-low power (ULP) 2.4 GHz RF front-end which consists of a low noise amplifier (LNA) and a passive mixer in a standard 65nm CMOS is presented. LNA adopts a complementary input stage and a current reused 2nd gain stage to achieve a high gain under a low power dissipation with an added linearization method. RF Down-conversion is implemented with a highly linearized complementary passive mixer adopting transmission gate type switches.
With fully on-chip components, the front-end achieves 23 dB conversion gain, 8 dB NF, -36 dBm P1dB and -21 dBm IIP3 while dissipating a 64 uW power from a 0.6 V supply voltage. LNA achieves a high voltage gain of 26.3 dB and minimum NF of 5.5 dB with a P1dB of -27 dBm and IIP3 of -13 dBm."
            ["sessionId"]=>
            string(38) "f236a33c-af8a-4277-83bf-7af5e5549069-5"
            ["presenter"]=>
            string(18) "Anjana Dissanayake"
            ["presenter_org"]=>
            string(50) "Korea Advanced Institute of Science and Technology"
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
        }
        ["start_time_num"]=>
        int(1496669400)
        ["stop_time_num"]=>
        int(1496675400)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO3B"
        ["title"]=>
        string(81) "Next Generation Transmitters and Receivers for Cellular and Wireless Connectivity"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(11) "Julian Tham"
        ["chair2"]=>
        string(15) "Yuan-Hung Chung"
        ["chair_org"]=>
        string(27) "Cypress Semiconductor Corp."
        ["chair_org2"]=>
        string(14) "MediaTek, Inc."
        ["sessionId"]=>
        string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(374) "This session covers next generation transmitter and receiver architectures for Cellular and Wireless Connectivity applications.  Three papers present various digital techniques for transmitters. A cellular receiver design supporting 5CC carrier aggregation and a WiFi transceiver design with integrated power amplifiers for 160MHz 802.11ac are presented in two other papers."
        ["child_sessions"]=>
        array(5) {
          ["MO3B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(99) "A Wideband Linear Direct Digital RF Modulator Using Harmonic Rejection and I/Q-Interleaving RF DACs"
            ["authors"]=>
            string(103) "Mohammadreza Mehrpoo, Mohsen Hashemi, Yiyu Shen, Rene van Leuken, Morteza S. Alavi, Leo C. N. de Vreede"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491537616"
            ["abstract"]=>
            string(643) "This paper presents a wideband linear direct digital RF modulator (DDRM) in 40 nm CMOS technology. It features an advanced 2nd-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2x9-bit DDRM core occupies 0.21mm2 and consumes only 110 mW at 1 GHz. Within the 0.9-3.1 GHz frequency range, the peak output power reaches +9.2 dBm and the 3rd/5th harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, -44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than -30 dB and -45 dB, respectively, and ACPR remains as low as -44 dBc up to a wide bandwidth of 110 MHz."
            ["sessionId"]=>
            string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-1"
            ["presenter"]=>
            string(20) "Mohammadreza Mehrpoo"
            ["presenter_org"]=>
            string(25) "Delft Univ. of Technology"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3B-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(114) "A Dual Core Power Combining Digital Power Amplifier for 802.11b/g/n with +26.8dBm Linear Output Power in 28nm CMOS"
            ["authors"]=>
            string(135) "Alden Wong, Philip Godoy, Ovidiu Carnu, Hao Li, Xingliang Zhao, Ashkan Olyaei, Amir Ghaffari, Sai-Wang Tam, Renaldi Winoto, Randy Tsang"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491537616"
            ["abstract"]=>
            string(566) "This paper presents a digital power amplifier with two cores that are power combined for a Psat of +32.5dBm. Assisted by an on-chip digital pre-distortion, a transmitted output power of +26.8dBm for 802.11g 54 Mbps 64-QAM is achieved. This is the highest reported linear output power for a digital power amplifier designed for 802.11b/g/n applications in bulk 28nm CMOS. A total area of 0.36mm^2 is used for the power amplifier cores and combiner. Drawing off of a 3.3V supply, this power amplifier has a drain efficiency of 21.2% at the maximum linear output power."
            ["sessionId"]=>
            string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-2"
            ["presenter"]=>
            string(10) "Alden Wong"
            ["presenter_org"]=>
            string(27) "Marvell Semiconductor, Inc."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(62) "A Fully-Integrated Digital-Intensive Polar Doherty Transmitter"
            ["authors"]=>
            string(137) "Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Michael Polushkin, Lei Zhou, Mustafa Acar, Rene van Leuken, Morteza Alavi, Leo de Vreede"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491537616"
            ["abstract"]=>
            string(697) "This paper presents an advanced 2.3-2.8 GHz fully-integrated digital-intensive polar Doherty transmitter realized in 40nm standard CMOS. The proposed architecture comprises CORDIC, digital delay aligners, interpolators, digital pre-distortion (DPD) circuitry in combination with frequency-agile wideband phase modulators followed by the digital main and peak power amplifier (PA) operating in quasi-load insensitive class-E using an on-chip power combiner. At 2.5 GHz, its maximum output power is 21.4 dBm. Drain efficiency is 49.4% at peak power, and 33.7% at 6-dB power back-off. Applying DPD for a 20MHz 64-QAM signal, the measured EVM is better than -30 dB while the average efficiency is 24%."
            ["sessionId"]=>
            string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-3"
            ["presenter"]=>
            string(9) "Yiyu Shen"
            ["presenter_org"]=>
            string(25) "Delft Univ. of Technology"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(84) "A 2x2 802.11ac WiFi Transceiver Supporting Per Channel 160MHz Operation in 28nm CMOS"
            ["authors"]=>
            string(291) "Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, Wen-Ming Chang, Chang-Ming Lai, Tao Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, Wei-Hsiu Hsu, Jing-Hong Zhan"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491537616"
            ["abstract"]=>
            string(417) "This paper presents a dual-band 2x2 WiFi transceiver in 28nm bulk CMOS. Achieved receiver and transmitter EVM floor at 5GHz for 160MHz per channel are -35dB and -33dB, respectively. The 2.4GHz integrated PA provides 26.5dBm saturated output power while its 5GHz counterpart delivers 26dBm. The 2.4GHz receiver features mixer first architecture while the transmitter includes a 2nd harmonic notch for emission control."
            ["sessionId"]=>
            string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-4"
            ["presenter"]=>
            string(14) "Jing-Hong Zhan"
            ["presenter_org"]=>
            string(14) "MediaTek, Inc."
            ["presenter_country"]=>
            string(6) "Taiwan"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3B-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3B"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(129) "A Current-Efficient Wideband Cellular RF Receiver for Multi-Band Inter- and Intra-Band Carrier Aggregation Using 14nm FinFET CMOS"
            ["authors"]=>
            string(143) "Youngmin Kim, Pilsung Jang, Taehwan Jin, Jaeseung Lee, Heeseon Shin, Suseob Ahn, Jungyeol Bae, Junghwan Han, Seungchan Heo, Thomas Byunghak Cho"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
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            string(4) "1330"
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            ["updated"]=>
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            ["abstract"]=>
            string(718) "A wideband cellular RF receiver for multi-band carrier aggregation employing a current-efficient wideband low noise amplifier and a frequency-band switchable transformer is demonstrated in a 14nm FinFET CMOS technology. The proposed wideband low-noise amplifier can support multiple-channel RF signals for intra-band carrier aggregation with high performance and low DC current consumption. Moreover, the frequency-band switchable transformer is used to support a size-efficient receiver up to 5 carrier components carrier aggregation. The receiver operates at frequencies between 0.6 to 2.7 GHz. The receiver has conversion gain more than 62 dB and noise figure less than 5 dB at all carrier aggregation combinations."
            ["sessionId"]=>
            string(38) "1b72ad25-c3ca-404b-9887-0b062e952c44-5"
            ["presenter"]=>
            string(12) "Youngmin Kim"
            ["presenter_org"]=>
            string(29) "Samsung Electronics Co., Ltd."
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496669400)
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            string(2) "13"
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        ["start_time_num"]=>
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        ["stop_time_num"]=>
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      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO3D"
        ["title"]=>
        string(21) "X Band PAs and Beyond"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(15) "Jeffrey Walling"
        ["chair2"]=>
        string(16) "Ranjit Gharpurey"
        ["chair_org"]=>
        string(13) "Univ. of Utah"
        ["chair_org2"]=>
        string(24) "Univ. of Texas at Austin"
        ["sessionId"]=>
        string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(211) "This session describes an array of techniques to address the challenges of operating PAs at high frequencies and wide bandwidths. These capabilities will serve as enablers for emerging 5G communications systems."
        ["child_sessions"]=>
        array(5) {
          ["MO3D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(116) "Fully Integrated CMOS X-Band Power Amplifier Quad With Current Reuse and Dynamic Digital Feedback (DDF) Capabilities"
            ["authors"]=>
            string(41) "Florian Bohn, Behrooz Abiri, Ali Hajimiri"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
            ["stop"]=>
            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(602) "A 10GHz fully-integrated stacked PA quad with dynamic digital feedback and control loops provides total output power of 200mW at 37% PAE. It utilizes data provided by multiple on-chip sensors to maintain safe operating conditions and regulate the individual power PA power supply voltages and independent power control for each PA. This digitally controlled stacked PA quad with on-chip matching allows higher operation voltages while maintaining current consumption constant, leading to higher overall system efficiency, as ohmic drop losses under large supply-to-breakdown voltage ratios are reduced."
            ["sessionId"]=>
            string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-1"
            ["presenter"]=>
            string(12) "Florian Bohn"
            ["presenter_org"]=>
            string(34) "California Institute of Technology"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO3D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(120) "A 42-46.4% PAE Continuous Class-F Power Amplifier With Cgd Neutralization at 26-34 GHz in 65 nm CMOS for 5G Applications"
            ["authors"]=>
            string(66) "Sheikh Nijam Ali, Pawan Agarwal, Shahriar Mirabbasi, Deukhyoun Heo"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
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            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(976) "This paper presents a wideband high efficiency continuous class-F (CCF) power amplifier (PA) at mm-Wave frequencies. A tuned load with a high-order harmonic resonance network is used to shape the current and voltage waveforms for the proposed CCF CMOS PA. Further, a transformer with a tuneable coupling coefficient (ktune) is incorporated in the tuned load network to address the detrimental feedback effect caused by the increased transistor gate-drain capacitance (Cgd) in deep submicron CMOS technology. This technique allows precise neutralization of Cgd, reducing undesirable influence on the tuned load, and maximizing power-efficiency and stability. The CCF PA prototype, implemented in 65 nm CMOS exhibits more than 42% power added efficiency (PAE) over 8 GHz bandwidth (26-34 GHz), while delivering saturated output power (Psat) of 14.75 dBm at 30 GHz. This design presents one of the highest reported PAEs among mm-Wave CMOS PAs, achieving 46.4% peak PAE at 29 GHz."
            ["sessionId"]=>
            string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-2"
            ["presenter"]=>
            string(16) "Sheikh Nijam Ali"
            ["presenter_org"]=>
            string(22) "Washington State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
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            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
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            string(2) "10"
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          ["MO3D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(71) "Waveform Engineering in a mm-Wave Stacked-HBT Switching Power Amplifier"
            ["authors"]=>
            string(28) "Kunal Datta, Hossein Hashemi"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
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            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(725) "A new family of hybrid stacked Class-K amplifiers are presented where each of the series stacked transistors can operate independently as different class of switching amplifiers. The voltage and current waveforms of the stacked transistors are shaped by independent harmonic load networks connected to the collector nodes of each of the stacked HBTs. A properly-designed Class-K amplifier can simultaneously achieve the high efficiency of Class-E/F amplifiers, high output power of Class-EF amplifiers, and high power gain of Class-E amplifiers. A proof-of-concept two-stage two-stacked balanced Class-K amplifier implemented in a 0.18 um SiGe HBT BiCMOS process demonstrates 25.5 dBm output power and 26% peak PAE at 34 GHz."
            ["sessionId"]=>
            string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-3"
            ["presenter"]=>
            string(11) "Kunal Datta"
            ["presenter_org"]=>
            string(28) "Univ. of Southern California"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
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            int(1496675400)
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            string(2) "15"
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          ["MO3D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(70) "Linear CMOS Power Amplifier at Ka-Band With Ultra-Wide Video Bandwidth"
            ["authors"]=>
            string(92) "Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, Juho Son, Bumman Kim"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
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            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(751) "A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental nonlinear mixing. The PA, composed of 3 cascaded common-source (CS) stages, achieves peak PAE of 21.8% at output power of 14 dBm with 22 dB gain. The 3rd order inter-modulation distortion (IMD3) at an output power of 5 dBm is under -30 dBc for a video bandwidth of 1 GHz. The PA and LDO are fabricated in a 65 nm CMOS process and occupy 0.53 mm2."
            ["sessionId"]=>
            string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-4"
            ["presenter"]=>
            string(13) "Daechul Jeong"
            ["presenter_org"]=>
            string(38) "Pohang Univ. of Science and Technology"
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
            ["stop_m"]=>
            string(2) "10"
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          ["MO3D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO3D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(108) "Adaptive Gain and Phase Adjustment for Local Linearization of Power Amplifiers of Micro/MM-Wave Phase Arrays"
            ["authors"]=>
            string(50) "Farid Shirinfar, Reza Rofougaran, Sudhakar Pamarti"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1330"
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            string(4) "1510"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(503) "A wideband, local Power Amplifier (PA) linearization technique is presented.  The proposed Adaptive Gain and Phase Adjustment (AGPA) local linearization technique compensates for both AM-AM and AM-PM distortion of PA for large channel bandwidths of hundreds of megahertz. A 60GHz PA designed in a 28nm CMOS process is designed and measured.  AGPA improves the OP1dB of the stacked PA by 2.8dB from 9.5dBm to 12.3dBm and reduces the IM3 products by 3dB with a tone spacing of 200MHz at 8dBm output power."
            ["sessionId"]=>
            string(38) "0976b7b2-a8dd-4c0b-81f4-0e1ad6c7e195-5"
            ["presenter"]=>
            string(15) "Farid Shirinfar"
            ["presenter_org"]=>
            string(32) "Univ. of California, Los Angeles"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496669400)
            ["start_h"]=>
            string(2) "13"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496675400)
            ["stop_h"]=>
            string(2) "15"
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            string(2) "10"
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        }
        ["start_time_num"]=>
        int(1496669400)
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        int(1496675400)
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    }
    ["15:30 - 17:10"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO4A"
        ["title"]=>
        string(22) "Low-Power Transceivers"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(13) "Gernot Hueber"
        ["chair2"]=>
        string(12) "Yao-Hong Liu"
        ["chair_org"]=>
        string(18) "NXP Semiconductors"
        ["chair_org2"]=>
        string(4) "IMEC"
        ["sessionId"]=>
        string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(355) "Wireless transceivers are one of the most power-consuming building blocks in IoT sensor nodes. In this session, several low-power transceiver design techniques will be presented, including crystal-less and stacked-RF designs.
In addition, three fully-integrated RF transceivers for emerging IoT standards, IEEE802.11ah and NFC-ISO/IEC1443, will be shown."
        ["child_sessions"]=>
        array(5) {
          ["MO4A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4A"
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            string(1) "1"
            ["paper_title"]=>
            string(48) "Crystal-Free Narrow-Band Radios for Low-Cost IoT"
            ["authors"]=>
            string(113) "Brad Wheeler, Filip Maksimovic, Nima Baniasadi, Sahar Mesri, Osama Khan, David Burnett, Ali Niknejad, Kris Pister"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(783) "A transceiver was designed and fabricated in 65 nm CMOS to verify the feasibility of using a free running, fully on-chip LC tank as the local oscillator in an IEEE 802.15.4 transceiver. This work aims to show that the elimination of the off-chip frequency reference is possible while still using a standards based narrow-band architecture. A free running LC tank is shown to have frequency stability better than 40 ppm in the absence of temperature changes. Demodulator-based feedback is implemented to track transmitter drift from slowly varying environmental factors and phase noise to within a standard deviation of 39 kHz from the set point. The modulation accuracy of a free-running open loop MSK transmitter is also investigated for suitability in an IEEE 802.15.4 transceiver."
            ["sessionId"]=>
            string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-1"
            ["presenter"]=>
            string(12) "Brad Wheeler"
            ["presenter_org"]=>
            string(29) "Univ. of California, Berkeley"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(61) "A 4mW-RX 7mW-TX IEEE 802.11ah Fully-Integrated RF Transceiver"
            ["authors"]=>
            string(178) "Ao Ba, Kia Salimi, Paul Mateman, Pepijn Boer, Johan van den Heuvel, Jordy Gloudemans, Johan Dijkhuis, Ming Ding, Yao-Hong Liu, Christian Bachmann, Guido Dolmans, Kathleen Philips"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(643) "An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this receiver achieves -104dBm sensitivity in the 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils the adjacent channel rejection requirements with at least 12dB margin. The digital polar transmitter achieves -30dB EVM and 10dB spectral mask margin."
            ["sessionId"]=>
            string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-2"
            ["presenter"]=>
            string(5) "Ao Ba"
            ["presenter_org"]=>
            string(12) "Holst Centre"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(115) "A Sub-1V, 2.8dB NF, 475µW Coupled LNA for Internet of Things Employing Dual-Path Noise & Nonlinearity Cancellation"
            ["authors"]=>
            string(33) "Mustafijur Rahman, Ramesh Harjani"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
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            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(451) "A 0.7V low power LNA uses a 1:3 frontend balun to achieve dual-mode noise and non-linearity cancellation which results in lowered power while improving performance. Noise and non-linearity of both the main and the auxiliary paths are mutually cancelled minimizing overall power consumption. The 2.8dB NF, -10.7dBm IIP3 LNA in TSMC's 65nm GP process consumes 475uW of power resulting in an FOM of 28.8dB which is 8.2dB better than the state of the art."
            ["sessionId"]=>
            string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-3"
            ["presenter"]=>
            string(17) "Mustafijur Rahman"
            ["presenter_org"]=>
            string(31) "Univ. of Minnesota, Twin Cities"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
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            string(2) "15"
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            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
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          ["MO4A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(89) "A Fully Integrated Reconfigurable Low-Power Sub-GHz Transceiver for 802.11ah in 65nm CMOS"
            ["authors"]=>
            string(83) "Meng Wei, Zheng Song, Peiyi Li, Jianfu Lin, Junfeng Zhang, Jiachen Hao, Baoyong Chi"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
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            string(1) "0"
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            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(696) "A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah is presented. The receiver uses the low-IF/zero-IF reconfigurable architecture to support 1/2/8MHz signal bandwidth, and the number of the Op-Amps in the analog baseband is reduced to 3 while providing 4th-order channel filtering and programmable gain amplification. The transmitter uses the digital polar architecture, with the open-loop phase modulator to support wide signal bandwidth and the inverse Class-D digital power amplifier to enhance the power efficiency. A Class-C VCO with dynamic gate bias technique is used in the fractional-N PLL frequency synthesizer. Implemented in 65nm CMOS, the receiver achieves "
            ["sessionId"]=>
            string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-4"
            ["presenter"]=>
            string(8) "Meng Wei"
            ["presenter_org"]=>
            string(14) "Tsinghua Univ."
            ["presenter_country"]=>
            string(5) "China"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
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            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
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          ["MO4A-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4A"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(57) "A 3.4Mbps NFC Card Emulator Supporting 40mm2 Loop Antenna"
            ["authors"]=>
            string(145) "Tieng Ying Choke, Ying Chow Tan, Chin Heng Leow, Junmin Cao, Liming Jin, Huajiang Zhang, Hon Cheong Hor, Eng Chuan Low, Weimin Shu, Osama Shana'a"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
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            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(948) "For compact integration of 13.56MHz NFC functionality in mobile devices, a small planar loop antenna is a necessity. Active load modulation (ALM) is a commonly adopted technique to boost load modulation amplitude to overcome weak inductive coupling in small antennas. However, due to the challenges of phase synchronization, ALM is mainly limited to low data rate NFC applications.  This paper describes the challenges of supporting NFC Very High Bit Rate (VHBR) Card Emulation Mode (PICC) in small antennas. An ultra fast-retimed phase synchronization PLL technique is proposed to overcome the technical challenges of ALM for high data rate uplink transmission. A sub-sampling ADC topology is implemented as VHBR ASK envelope demodulator. A clock extractor-based PLL provides precise synchronized continuous clock to the high speed sub-sampling ADC for accurate demodulation of all ASK envelopes with modulation index (MI) ranging from 8% to 100%."
            ["sessionId"]=>
            string(38) "0931a18e-86e5-479d-a3ea-a48aa92510af-5"
            ["presenter"]=>
            string(16) "Tieng Ying Choke"
            ["presenter_org"]=>
            string(29) "MediaTek, Singapore Pte. Ltd."
            ["presenter_country"]=>
            string(9) "Singapore"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
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            ["stop_h"]=>
            string(2) "17"
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        ["start_time_num"]=>
        int(1496676600)
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        int(1496682600)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO4B"
        ["title"]=>
        string(62) "RF Circuits for Emrging Applications and Gigabit Optical Links"
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(8) "Fred Lee"
        ["chair2"]=>
        string(11) "Ayman Fayed"
        ["chair_org"]=>
        string(12) "Google, Inc."
        ["chair_org2"]=>
        string(16) "Ohio State Univ."
        ["sessionId"]=>
        string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(643) "The first three presentations cover new applications of RF circuit design.  First, an RFDAC is designed in a FINFET process and tackles challenging mismatch issues.  Next, a galvanic isolator using lateral RF coupling techniques achieves 3.3kVrms isolation.  Finally, an implantable RF bio-sensing interface chip is designed using optical and RF backscatter techniques.
The final two papers focus on drivers for gigabit optical links.  A SiGe linear modulator driver is presented which achieves 4.8-Vpp differential swing for rates up to 120 GBaud.  The final paper presents a 15 Gbaud PAM4 laser driver with active termination in 65-nm CMOS."
        ["child_sessions"]=>
        array(5) {
          ["MO4B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(108) "A 12-b, 1-GS/s 6.1 mW Current-Steering DAC in 14 nm FinFET With 80 dB SFDR for 2G/3G/4G Cellular Application"
            ["authors"]=>
            string(85) "Jaekwon Kim, Woojin Jang, Yanghun Lee, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491969619"
            ["abstract"]=>
            string(683) "A 14nm FinFET CMOS 12-b current-steering digital-to-analog (DAC) for 2G/3G/4G cellular applications is presented. A bit segmentation of 6-bit thermometer and 6-bit binary is adopted, and it utilizes the dynamic element matching (DEM) technique to suppress the spurious tones caused by the current source mismatches in 3-D FinFETs. In addition, to keep the voltage drop across each transistor within long-term reliability limit, output switches are designed with shielding transistors while achieving make-before-break operation with the proposed low crossing point level shifter. The active area of a single DAC is 0.036 mm², and its power consumption is 6.1 mW with SFDR of 80 dBc."
            ["sessionId"]=>
            string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-1"
            ["presenter"]=>
            string(11) "Jaekwon Kim"
            ["presenter_org"]=>
            string(29) "Samsung Electronics Co., Ltd."
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4B-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(103) "CMOS Integrated Galvanically Isolated RF Chip-to-Chip Communication Utilizing Lateral Resonant Coupling"
            ["authors"]=>
            string(59) "Mahdi Javid, Richard Burton, Karel Ptacek, Jennifer Kitchen"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491969619"
            ["abstract"]=>
            string(1081) "In this work, a high voltage galvanically isolated chip-to-chip communication circuit utilizing laterally coupled resonators is reported. The adjacently placed resonators provide high voltage galvanic isolation (GI) using horizontal space between resonators filled with oxide, which minimizes the need for thick inter-metal dielectrics. A previously unexplored application for lateral coupling is introduced. Magnetic coupling between resonators is used to transfer an upconverted digitally-modulated OOK control signal at 2.8 GHz through the galvanic isolator. This proposed method can be integrated using CMOS processes, without altering the native process or adding extra fabrication steps. The system is realized in a 0.25 m BCD (Bipolar-CMOS-DMOS) process with only four metal layers for proof of concept. The design does not require exotic packaging and provides 3.3kV RMS isolation, small physical area of 0.95mm2, and sub-20ns propagation delay. The implemented resonators inherently act as bandpass filters, thus enhancing circuit noise immunity to common mode transients."
            ["sessionId"]=>
            string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-2"
            ["presenter"]=>
            string(11) "Mahdi Javid"
            ["presenter_org"]=>
            string(19) "Arizona State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(96) "A 200µm x 200µm x 100µm, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless Bio-Sensing System"
            ["authors"]=>
            string(207) "Stephen O'Driscoll, Sean Korhummel, Peng Cong, Kannan Sankaragomathi, You Zou, Jiang Zhu, Travis Deyle, Alireza Dastgheib, Bo Lu, Michael Tierney, Jingru Shao, Christian Gutierrez, Stephen Jones, Haunfen Yao"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491969619"
            ["abstract"]=>
            string(509) "A wireless system-on-chip with integrated antenna, power harvesting and biosensors is presented that is small enough, 200µm x 200µm x 100µm, to allow painless injection. Small device size is enabled by: a 13µm x 20µm 1nA current reference; optical clock recovery; low voltage inverting dc-dc to enable use of higher quantum efficiency diodes; on-chip resonant 2.4GHz antenna; and array scanning reader. In-vivo power and data transfer is demonstrated and linear glucose concentration recordings reported."
            ["sessionId"]=>
            string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-3"
            ["presenter"]=>
            string(18) "Stephen O'Driscoll"
            ["presenter_org"]=>
            string(29) "Verily (Google) Life Sciences"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(102) "SiGe BiCMOS Linear Modulator Drivers With 4.8-Vpp Differential Output Swing for 120-GBaud Applications"
            ["authors"]=>
            string(59) "Robert Baker, James Hoffman, Peter Schvan, Sorin Voinigescu"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491969619"
            ["abstract"]=>
            string(476) "Two linear, large-swing distributed amplifiers (DAs) are reported for future 120-GBaud fiber-optic systems. The measured differential gain and bandwidth are over 20 dB and 70 GHz, respectively, and the P1dB is -2 dBm. Eye diagram measurements with at least 4.8-Vpp differential swing were performed for NRZ signals up to a record 120 Gb/s, and with 4-PAM and 8-PAM signals up to 64 GBaud, with the symbol rate limited by the speed and ENOB of the arbitrary waveform generator."
            ["sessionId"]=>
            string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-4"
            ["presenter"]=>
            string(12) "Robert Baker"
            ["presenter_org"]=>
            string(16) "Univ. of Toronto"
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4B-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4B"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(87) "A 32Gb/s-NRZ, 15GBaud/s-PAM4 DFB Laser Driver With Active Back-Termination in 65nm CMOS"
            ["authors"]=>
            string(173) "Bozhi Yin, Nan Qi, Jingbo Shi, Xi Xiao, Daigao Chen, Miaofeng Li, Zhiyong Li, Jiangbing Du, Zuyuan He, Rui Bai, Yi Wang, Jun Zheng, Fred Chang, Huanlin Zhang, Patrick Chiang"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491969619"
            ["abstract"]=>
            string(707) "A 32Gb/s-NRZ, 15GBaud/s-PAM4 configurable DFB Laser Diode Driver (LDD) is presented in standard 65nm CMOS. The driver employs a balanced-input, single-ended-output topology to deliver large current output, and integrates a tunable pre-emphasis to extend the bandwidth. An on-chip active back-termination (ABT) is proposed which absorbs loading reflections without sacrificing the effective modulation current. Directly wire-bonded to a DFB laser chip, the measurement results show 25.78Gb/s NRZ optical eye-diagram with 4dB Extinction Ratio (ER) and a 19.3% eye-mask margin referred to the 100G specification. The LDD delivers 60mA bias and 60mApp modulation current, consuming only 550mW power consumption."
            ["sessionId"]=>
            string(38) "fd78dec0-8961-4789-8041-250e0ab16aab-5"
            ["presenter"]=>
            string(9) "Bozhi Yin"
            ["presenter_org"]=>
            string(11) "Fudan Univ."
            ["presenter_country"]=>
            string(5) "China"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
        }
        ["start_time_num"]=>
        int(1496676600)
        ["stop_time_num"]=>
        int(1496682600)
      }
      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "MO4D"
        ["title"]=>
        string(35) "Reconfigurable Receiver Front-Ends "
        ["date"]=>
        string(19) "Monday, 5 June 2017"
        ["chair"]=>
        string(15) "Eric Klumperink"
        ["chair2"]=>
        string(14) "Ramesh Harjani"
        ["chair_org"]=>
        string(15) "Univ. of Twente"
        ["chair_org2"]=>
        string(18) "Univ. of Minnesota"
        ["sessionId"]=>
        string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(393) "Various novel analog and digital techniques that are employed in the realization of reconfigurable RF front-ends will be presented. These allow for high blocker and self-interference resiliency, full-duplex operation, and efficient use of power and silicon area.  Examples include use of non-reciprocal elements, mixer-first receiver innovations, code domain operation and compressive sensing."
        ["child_sessions"]=>
        array(5) {
          ["MO4D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(122) "A Direct RF-to-Information Converter for Reception and Wideband Interferer Detection Employing Pseudo-Random LO Modulation"
            ["authors"]=>
            string(114) "Tanbir Haque, Mathew Bajor, Yudong Zhang, Jianxun Zhu, Zarion Jacobs, Robert Kettlewell, John Wright, Peter Kinget"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(710) "The Direct RF-to-information Converter (DRF2IC) unifies high sensitivity signal reception, narrowband spectrum sensing and energy-efficient wideband interferer detection into a fast-reconfigurable and easily
scalable architecture. In reception mode, the DRF2IC RF front-end (RFFE) consumes 46.5mW and delivers 40MHz RF bandwidth, 41.5dB conversion gain, 3.6dB NF and -2dBm B1dB. 72dB out-of-channel blocker rejection is achieved in narrowband sensing mode. In compressed sensing wideband interferer detection mode, 66dB operational dynamic range, 40dB instantaneous dynamic range, 1.43GHz instantaneous bandwidth is demonstrated and 6 interferers scattered over 1.26GHz are detected in 1.2uS consuming 58.5mW."
            ["sessionId"]=>
            string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-1"
            ["presenter"]=>
            string(12) "Tanbir Haque"
            ["presenter_org"]=>
            string(14) "Columbia Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(90) "A 0.3 GHz to 1.4 GHz N-Path Mixer-Based Code-Domain RX With TX Self-Interference Rejection"
            ["authors"]=>
            string(32) "Abhishek Agrawal, Arun Natarajan"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(751) "A code-domain N-path RX is proposed based on PN-code modulated LO pulses for concurrent reception of two code-modulated signals. Additionally, a combination of Walsh-Function and PN sequence is proposed to translate in-band TX self-interference (SI) to out-of-band at N-path RX output enabling frequency filtering for high SI rejection. A 0.3 GHz-1.4 GHz 65-nm CMOS implementation has 35 dB gain for desired signals and concurrently receives two RX signals while rejecting mismatched spreading codes at RF input. Proposed TX SI mitigation approach results in 38.5 dB rejection for -11.8 dBm 1.46 Mb/s QPSK modulated SI at RX input. The RX achieves 23 dBm OP1dB with respect to in-band SI, while consuming ∼35mW and occupying 0.31 sq. mm of die area."
            ["sessionId"]=>
            string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-2"
            ["presenter"]=>
            string(16) "Abhishek Agrawal"
            ["presenter_org"]=>
            string(18) "Oregon State Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(96) "A 0.7 to 1 GHz Switched-LC N-Path LNA Resilient to FDD-LTE Self-Interference at ≥40 MHz Offset"
            ["authors"]=>
            string(73) "Gengzhen Qi, Barend van Liempd, Pui-In Mak, Rui P. Martins, Jan Craninckx"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(630) "This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB1dB) at ≥40MHz offset and 6.8dB blocker NF at +4dBm blocker power for the default mode, while consuming a reasonable power of 48.4 to 62.5mW. When reconfigured to the high-rejection mode, the LNA offers a tunable cancellation notch improving the output rejection to >50dBc."
            ["sessionId"]=>
            string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-3"
            ["presenter"]=>
            string(11) "Gengzhen Qi"
            ["presenter_org"]=>
            string(19) "University Of Macau"
            ["presenter_country"]=>
            string(5) "China"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(107) "A Mixer-First Receiver with Enhanced Selectivity by Capacitive Positive Feedback Achieving +39dBm IIP3 and "
            ["authors"]=>
            string(74) "Yuanching Lien, Eric Klumperink, Bernard Tenbroek, Jon Strange, Bram Nauta"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(703) "A mixer-first receiver enhanced with capacitive positive feedback is proposed to obtain a steeper filter roll-off and enhanced linearity, while keeping low noise figure. It covers all sub-6GHz cellular bands and achieves a high IIP3 of +39dBm, IIP2 of +88dBm and blocker 1dB gain compression point of +12dBm for a blocker frequency-offset of 80MHz at LO=2GHz. The NF ranges from 2.4dB at LO=1GHz to 5.4dB at LO=6GHz. The measured blocker NF for LO=1.4GHz degrades only from 2.5dB to 4.7dB at 0dBm blocker power with frequency-offset of 80MHz. The chip has been fabricated in Globalfoundries 45nm SOI technology on a high resistivity substrate. The active area is 1000umx800um and supply voltage is 1.2V."
            ["sessionId"]=>
            string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-4"
            ["presenter"]=>
            string(14) "Yuanching Lien"
            ["presenter_org"]=>
            string(15) "Univ. of Twente"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
          ["MO4D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "MO4D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(102) "85-110 GHz CMOS Tunable Nonreciprocal Transmission Line With 45 dB Isolation for Wideband Transceivers"
            ["authors"]=>
            string(20) "Chang Yang, Ping Gui"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1530"
            ["stop"]=>
            string(4) "1710"
            ["date"]=>
            string(19) "Monday, 5 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(681) "The first CMOS nonreciprocal transmission line (TL) for wideband tunable full-duplex transceiver front ends, having over 45 dB isolation in a bandwidth of 1.5 GHz and tuning range of 85-110 GHz, is demonstrated. Offering tunable nonreciprocal propagation, this structure is based on a parametric time-varying TL modulated by a 10 GHz signal through distributed capacitive mixing. Two capacitive mixers together with a biasing network form a resonant type of wideband matching. Implemented in a chip area of 0.245 mm2 in 65 nm CMOS, this nonreciprocal TL achieves over 45 dB isolation throughout its entire bandwidth, a maximum 6.5 dB insertion loss (IL) and over 10 dB return loss."
            ["sessionId"]=>
            string(38) "eeecdd4f-704f-4146-9fdf-db7c168037b9-5"
            ["presenter"]=>
            string(10) "Chang Yang"
            ["presenter_org"]=>
            string(24) "Southern Methodist Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496676600)
            ["start_h"]=>
            string(2) "15"
            ["start_m"]=>
            string(2) "30"
            ["stop_time_num"]=>
            int(1496682600)
            ["stop_h"]=>
            string(2) "17"
            ["stop_m"]=>
            string(2) "10"
          }
        }
        ["start_time_num"]=>
        int(1496676600)
        ["stop_time_num"]=>
        int(1496682600)
      }
    }
  }
  ["Tuesday (6th)"]=>
  array(3) {
    ["8:00 - 9:40"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU1A"
        ["title"]=>
        string(28) "RF Front-End Building Blocks"
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(10) "Gary Zhang"
        ["chair2"]=>
        string(16) "Bodhisatwa Sadhu"
        ["chair_org"]=>
        string(29) "Guangdong Univ. of Technology"
        ["chair_org2"]=>
        string(31) "IBM T.J. Watson Research Center"
        ["sessionId"]=>
        string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(324) "In this session, various RF front-end building blocks such as mixers, filters and phase shifters are discussed. Furthermore, advanced techniques such as harmonic rejection and feed-forward linearization are presented. These components and techniques are applicable to phased arrays, MIMO systems and highly linear receivers."
        ["child_sessions"]=>
        array(5) {
          ["TU1A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1A"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(98) "A Bi-Directional, X-Band 6-Bit Phase Shifter for Phased Array Antennas Using an Active DPDT Switch"
            ["authors"]=>
            string(39) "Yunyi Gong, Moon-Kyu Cho, John Cressler"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(615) "This paper presents an X-band 6-bit phase shifter using active bi-directional double-pole, double-throw (DPDT) switches. The phase shifter is implemented in a 130-nm SiGe BiCMOS technology. Three additional tuning bits are included in the design to achieve accurate phase shifting performance. The phase shifter demonstrates a > 11.5-dB gain in both directions of operation over the 8-12 GHz frequency range, with an RMS amplitude error < 0.9 dB, an RMS phase error < 2.2º, a return loss > 10 dB and an input-referred 1 dB compression point of -15 dBm. The circuit has dimensions of 2.6 × 1.5 mm2, including pads."
            ["sessionId"]=>
            string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-1"
            ["presenter"]=>
            string(10) "Yunyi Gong"
            ["presenter_org"]=>
            string(31) "Georgia Institute of Technology"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(131) "Low Power Highly Linear Band-Pass/Band-Stop Filter for 2-4 GHz With Less than 1% of Fractional Bandwidth in 0.13 um CMOS Technology"
            ["authors"]=>
            string(29) "Laya Mohammadi, Kwang-Jin Koh"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(640) "A low power highly linear active filter supporting both band-pass and band-stop modes is implemented in 0.13um CMOS. The frequency tunable (2-4GHz) active filter utilizes a linearized Q-boosting network and a liner varactor control scheme to mitigate linearity degradation when increasing filter Q. The BPF tolerates blockers to +16dBm 1 dB desentesization. In BPF mode, typical Q-tuning ranges 5-250, NF and IP-1dB are 4~5.2dB and -6~+3dBm ,respectively, resulting in a peak DR of 170 dB.Hz. In BSF mode, NF ranges 4~4.8dB and IP-1dB is -1.8~0dBm at 2.5-4GHz. Typical current consumption is 14-19 mA from 2 V supply. Chip size is 0.35 mm2."
            ["sessionId"]=>
            string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-2"
            ["presenter"]=>
            string(14) "Laya Mohammadi"
            ["presenter_org"]=>
            string(50) "Virginia Polytechnic Institute and State Universit"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(94) "A Feedforward Linearization Technique Implemented in IF Band for Active Down-Conversion Mixers"
            ["authors"]=>
            string(34) "Hao Li, Xiao Yang, Carlos Saavedra"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(714) "A feedforward linearization technique to cancel the third-order intermodulation (IM3) of the down-conversion mixers is proposed, in which a low-frequency second-order intermodulation tone (IM2) is created and multiplied by the mixer’s output to generate the IM3 tones for the cancellation. The proposed linearization technique is applied to an active mixer operating at 2 GHz. Fabricated in a 0.13-m CMOS process and operated at 1.2 V supply, the mixer with a unit-gain IF amplifier in series delivers 8.5 dB gain and 2.5 dBm IIP3 without linearization. The linearization technique achieves 12-dB IIP3 improvement with negligible gain reduction, less than 0.2 dB of noise penalty and an extra current of 4.2 mA."
            ["sessionId"]=>
            string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-3"
            ["presenter"]=>
            string(6) "Hao Li"
            ["presenter_org"]=>
            string(13) "Queen's Univ."
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(109) "A 1-30 GHz 3-Bit Vector Modulator Based on Ultra-Wideband IQ-Generation for MIMO-Radar-Systems in SiGe BiCMOS"
            ["authors"]=>
            string(57) "Benedikt Welp, Askold Meusling, Klaus Aufinger, Nils Pohl"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(779) "MIMO phased array radar systems benefit from beamforming in order to increase system dynamic and detection range. Therefore, an ultra-wideband IQ signal generation concept for driving a vector adder, which produces the desired phase shift in each channel of a MIMO phased array radar system, has been developed. The classic concept to generate wideband quadrature signals that uses a frequency doubler and a static frequency divider brings a 0°/180° phase uncertainty at the dividers outputs which makes this concept useless when using multiple TX-channels at once like in beamforming MIMO phased array radars. Therefore, the classical concept has been enhanced with two possible solutions which are presented in this work. The novel concepts are able to operate from 1-30 GHz."
            ["sessionId"]=>
            string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-4"
            ["presenter"]=>
            string(13) "Benedikt Welp"
            ["presenter_org"]=>
            string(14) "Fraunhofer FHR"
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1A-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1A"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(114) "A 0.05-6 GHz Voltage-Mode Harmonic Rejection Mixer With up to 30 dBm In-Band IIP3 and 35 dBc HRR in 32 nm SOI CMOS"
            ["authors"]=>
            string(31) "Kerim Kibaroglu, Gabriel Rebeiz"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(956) "This paper presents a new harmonic rejection mixer circuit that uses resistive scaling to achieve very high linearity and a harmonic rejection ratio greater than 35 dBc. The mixer employs 4 double-balanced mixers driven by 8 LO phases with 12.5% duty cycle to isolate different paths. The mixer switches have been implemented with thin- and thick- oxide transistors to improve linearity further at the cost of reduced tuning range. The measured conversion loss at an IF of 100 MHz is 6.6-10.8 dB and 6.4-9.2 dB for an RF of 0.05-6 GHz and 0.05-4 GHz, in-band IIP3 is 23-19 dBm and 31-21 dBm. The power consumption is 29-126 and 98-298 mW for thin-oxide and thick-oxide designs, respectively. To our knowledge, this is the highest linearity and widest tuning range reported to-date for a harmonic rejection mixer. Application areas are high-linearity wideband receivers, base-station, instrumentation receivers with reduced front-end filtering requirements."
            ["sessionId"]=>
            string(38) "93555d70-f0e5-4af3-ac21-4ab157181f30-5"
            ["presenter"]=>
            string(15) "Kerim Kibaroglu"
            ["presenter_org"]=>
            string(32) "Univ. of California at San Diego"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496736000)
        ["stop_time_num"]=>
        int(1496742000)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU1B"
        ["title"]=>
        string(35) "Advanced Mm-Wave Circuit Techniques"
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(8) "Hua Wang"
        ["chair2"]=>
        string(13) "Pierre Busson"
        ["chair_org"]=>
        string(31) "Georgia Institute of Technology"
        ["chair_org2"]=>
        string(18) "STMicroelectronics"
        ["sessionId"]=>
        string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(633) "This session presents advanced circuit techniques for basic building blocks in mm-wave and above systems. The first paper demonstrates a W-band CMOS amplifier with broadband neutralization technique operating at 0.5V supply. The second paper shows a 77GHz mm-Wave active reflector for vehicular radar and other applications. The third paper proposes an advanced broadband ESD protection design for mm-Wave front-end circuits. The fourth paper presents an in-antenna active power combining at 240GHz. The session is concluded with a mm-Wave transformer-based injection locking frequency divider (ILFD) in CMOS with 62.9% tuning range."
        ["child_sessions"]=>
        array(5) {
          ["TU1B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(54) "An 80-106 GHz CMOS Amplifier With 0.5 V Supply Voltage"
            ["authors"]=>
            string(118) "Kosuke Katayama, Shuhei Amakawa, Kyoya Takano, Takeshi Yoshida, Minoru Fujishima, Kazuya Hisamitsu, Hirotaka Takatsuka"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(685) "A low-power CMOS W-band amplifier that feeds on a 0.5-V supply is presented. It achieves a peak gain of 24.1 dB and consumes 12 mW. This was made possible by (a) the use of Mie Fujitsu Semiconductor 55-nm CMOS technology with deeply depleted channel (DDC) MOSFETs, which are meant specifically for ultralow-power designs with sub-1 V supply voltage, (b) high-fmax transistor layout, which gives about 1 dB higher gain in the W-band than the ordinary layout, and (c) single-ended negative-capacitance feedback technique, which gives wideband gain boosting comparable to its differential counterpart (with cross-coupled feedback capacitors) with half the power consumption of the latter."
            ["sessionId"]=>
            string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-1"
            ["presenter"]=>
            string(15) "Kosuke Katayama"
            ["presenter_org"]=>
            string(20) "Hiroshima University"
            ["presenter_country"]=>
            string(5) "Japan"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1B-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(56) "A 77-GHz Active Millimeter-Wave Reflector for FMCW Radar"
            ["authors"]=>
            string(46) "Sadegh Dadash, Juergen Hasch, Sorin Voinigescu"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(494) "An 18-mW active millimeter-wave reflector fabricated in 45-nm SOI CMOS technology exhibits a peak gain of 20 dB at 77 GHz, a 3-dB bandwidth of 5 GHz from 75.5 to 80.5 GHz, and a 50-Ohm noise figure of 7.5-8.5 dB over the same frequency band. It consists of an LNA, a BPSK modulator and two variable gain output stages each driving a separate transmit antenna. The chip occupies 570um x 880um and is flip-chip mounted on a 7mm x 7mm flexible interposer with two transmit and one receive antenna."
            ["sessionId"]=>
            string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-2"
            ["presenter"]=>
            string(13) "Sadegh Dadash"
            ["presenter_org"]=>
            string(16) "Univ. of Toronto"
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(100) "A High-Performance Slow-Wave CPW With ESD Protection for Ultraflat Band Millimeter-Wave Applications"
            ["authors"]=>
            string(68) "Wei Gao, Handoko Linewih, Suh-Fei Lim, Jian-Hsing Lee, Sern-Ee Leang"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(480) "A high performance Slow-Wave Coplanar Waveguide (CPW) with distributed small pieces of ESD diodes in advanced CMOS process is presented to match 50Ohm characteristic impedance. Optimized design of each segmented diode pairs and its Lateral Pickups experimentally achieves a very low RF loss of -1.55dB at 60GHz while passing at least 2.6kV HBM level. Its ultraflat frequency response up to 90GHz makes it also favourable for ultrafast digital I/Os with bit rate as high as 64Gb/s."
            ["sessionId"]=>
            string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-3"
            ["presenter"]=>
            string(7) "Wei Gao"
            ["presenter_org"]=>
            string(15) "GLOBALFOUNDRIES"
            ["presenter_country"]=>
            string(9) "Singapore"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(120) "Circuit Building Blocks for Efficient In-Antenna Power Combining at 240 GHz With non-50 Ohm Amplifier Matching Impedance"
            ["authors"]=>
            string(84) "Christian von Vangerow, Benjamin Goettel, Herman Ng, Dietmar Kissinger, Thomas Zwick"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(910) "In this work active and passive circuit components suitable for efficient in-antenna power combining are investigated with focus on the matching impedance between the individual components. In the proposed concept, the input power is split by 1:4 couplers with 12.5 Ω output impedance, which enables a very broadband input matching of the following amplifiers. To combine the output power of the parallelized amplifiers, an eight-feed integrated lens antenna (ILA) with 70 Ω input impedance is used, which allows for compact matching to the optimum load impedance of the amplifiers. All individual circuit components are realized in IHP's SG13G2 technology and show excellent agreement with the simulation results. The four times parallelized amplifier shows a gain of roughly 6 dB at 240 GHz excluding coupler losses and the realized antenna gain of the eight-feed ILA is about 15 dBi from 200 to 280 GHz."
            ["sessionId"]=>
            string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-4"
            ["presenter"]=>
            string(22) "Christian von Vangerow"
            ["presenter_org"]=>
            string(33) "Karlsruhe Institute of Technology"
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1B-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1B"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(94) "A 27.9-53.5-GHz Transformer-Based Injection-Locked  Frequency Divider With 62.9% Locking Range"
            ["authors"]=>
            string(59) "Jingzhi Zhang, Huihua Liu, Yunqiu Wu, Chenxi Zhao, Kai Kang"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(610) "An ultra-wide  locking range transformer-based injection-locked frequency divider (ILFD) is presented. By 
making use of a  4th-order transformer-based  resonator  and an inductive gain peaking technique, the proposed ILFD can achieve high performance in terms of wide locking range and low power consumption.  Fabricated in a standard 65nm CMOS process  with a core area of 0.18mm2, the ILFD measures a locking range of  62.9% from  27.9  to 53.5 GHz while consuming 5.8mW from a 1V power supply. Moreover, when  operating at 0.8V power supply, the proposed ILFD consumes only 3.2mW with 48.9% locking range."
            ["sessionId"]=>
            string(38) "ef1355d2-e7b4-4572-be76-faa994cf48d1-5"
            ["presenter"]=>
            string(13) "Jingzhi Zhang"
            ["presenter_org"]=>
            string(51) "Univ. of Electronic Science and Technology of China"
            ["presenter_country"]=>
            string(5) "China"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496736000)
        ["stop_time_num"]=>
        int(1496742000)
      }
      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU1D"
        ["title"]=>
        string(29) "Reconfigurable Multi-Mode PAs"
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(16) "Patrick Reynaert"
        ["chair2"]=>
        string(8) "Gary Hau"
        ["chair_org"]=>
        string(23) "Katholieke Univ. Leuven"
        ["chair_org2"]=>
        string(27) "Qualcomm Technologies, Inc."
        ["sessionId"]=>
        string(38) "e551e06c-1aa7-4b63-a015-805b71173023-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(204) "This session describes various techniques to improve PA performances over wide bandwidth and output power ranges. These architectures address the trade-off needed in current and next generation front-end."
        ["child_sessions"]=>
        array(5) {
          ["TU1D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(92) "A Digital mm-Wave PA Architecture With Simultaneous Frequency and Back-off Reconfigurability"
            ["authors"]=>
            string(47) "Chandrakanth Chappidi, Xue Wu, Kaushik Sengupta"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(942) "In this paper, we present a generalized network synthesis approach that enables both frequency and back-off reconfigurability in a mm-Wave power amplifier (PA) architecture to maintain high-efficiency operation with spectrally efficient codes across a wide frequency range.The method is based on the synthesis of an asymmetrical multi-port combiner network  that exploits the interaction of asymmetric mm-Wave DAC cells synthesizing the optimal impedance across the 2D space of reconfiguration: frequency and back-off. As a proof of concept, a silicon-based PA is presented which operates between 30-55 GHz with peak Psat of 23.7 dBm at 40 GHz and output drain efficiency of 34.5% and 22$% at the 0 and -6 dB back-off respectively. The PA maintains output drain efficiency>16% at -6 dB back-off across the range. Non-constant modulation is demonstrated with pulse shaping and with data rates upto 4 Gbps across the frequencies from 30-50 GHz."
            ["sessionId"]=>
            string(38) "e551e06c-1aa7-4b63-a015-805b71173023-1"
            ["presenter"]=>
            string(21) "Chandrakanth Chappidi"
            ["presenter_org"]=>
            string(15) "Princeton Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(82) "A Digitally-Tuned Triple-Band Transformer Power Combiner for CMOS Power Amplifiers"
            ["authors"]=>
            string(31) "Rahul Singh, Jeyanandh Paramesh"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(646) "This paper presents the design and implementation of a CMOS transformer combiner that can be reconfigured to have similar efficiencies at widely separated frequency bands. Conventional transformer combiners employ a fixed tuning capacitance in the secondary network to optimize the efficiency at a single frequency. In this work, we present a modified transformer combiner where digitally-switchable capacitors introduced at low-swing nodes within the combiner network enable frequency reconfiguration using CMOS switches. A 65 nm CMOS triple-band (2.5/3/3.5 GHz) power amplifier (PA) chip employing the reconfigurable combiner is also presented."
            ["sessionId"]=>
            string(38) "e551e06c-1aa7-4b63-a015-805b71173023-2"
            ["presenter"]=>
            string(11) "Rahul Singh"
            ["presenter_org"]=>
            string(21) "Carnegie Mellon Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(67) "A Split-Array, C-2C Switched-Capacitor Power Amplifier in 65nm CMOS"
            ["authors"]=>
            string(48) "Zhidong Bai, Wen Yuan, Ali Azam, Jeffrey Walling"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(771) "A multiphase RF, C-2C split-array switched-capacitor power amplifier (SCPA) is introduced that allows the resolution and quality factor of the SCPA to be independently controlled. This allows the SCPA to be designed up to the resolution limit of the process, as determined by capacitor matching and jitter in the clock. In prior SCPAs, the resolution was limited by the choice of the output matching network quality factor and the minimum sized capacitor available in the process. A split-array, C-2C SCPA is implemented in 65nm CMOS and occupies 1×2mm2. It delivers a peak output power of 24.05 dBm with a peak system efficiency (SE) of 40.6%. When transmitting a 1.4 MHz, 64 QAM LTE signal it outputs 18.8 dBm at 21.2% SE, with a measured EVM of 2.65 %-rms at 1.7 GHz."
            ["sessionId"]=>
            string(38) "e551e06c-1aa7-4b63-a015-805b71173023-3"
            ["presenter"]=>
            string(11) "Zhidong Bai"
            ["presenter_org"]=>
            string(13) "Univ. of Utah"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(92) "A 20dBm Outphasing Class E PA With High Efficiency at Power Back-off in 65nm CMOS Technology"
            ["authors"]=>
            string(45) "Ali Ghahremani, Anne-Johan Annema, Bram Nauta"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(533) "This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off."
            ["sessionId"]=>
            string(38) "e551e06c-1aa7-4b63-a015-805b71173023-4"
            ["presenter"]=>
            string(14) "Ali Ghahremani"
            ["presenter_org"]=>
            string(15) "Univ. of Twente"
            ["presenter_country"]=>
            string(15) "The Netherlands"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU1D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU1D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(97) "An S/X-Band CMOS Power Amplifier Using a Transformer-Based Reconfigurable Output Matching Network"
            ["authors"]=>
            string(36) "Jaeyong Ko, Sungho Lee, Sangwook Nam"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(3) "800"
            ["stop"]=>
            string(3) "940"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1490182690"
            ["abstract"]=>
            string(699) "A dual-band power amplifier (PA) with an integrated reconfigurable transformer is presented. The PA operating in the S/X-band is fully integrated using a 0.18-µm RF CMOS process. The switchable transformer is designed by tuning its primary winding and a shunt capacitor at 50Ω load with passive efficiency more than 62%/67% for S/X-band. The measurement results show saturated output power (Psat) of 24.3/21.2 dBm with peak drain efficiency (DE) of 34.8%/12.2% at 3.1/8.0 GHz, respectively. The 1-dB bandwidth is 0.7/1.25 GHz (2.8–3.5/7.5–8.75 GHz) for the S/X-band. This amplifier with the proposed transformer is suitable for use in an integrated dual-band high-resolution radar transceiver."
            ["sessionId"]=>
            string(38) "e551e06c-1aa7-4b63-a015-805b71173023-5"
            ["presenter"]=>
            string(10) "Jaeyong Ko"
            ["presenter_org"]=>
            string(20) "Seoul National Univ."
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496736000)
            ["start_h"]=>
            string(1) "8"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496742000)
            ["stop_h"]=>
            string(1) "9"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496736000)
        ["stop_time_num"]=>
        int(1496742000)
      }
    }
    ["10:00 - 11:40"]=>
    array(3) {
      [0]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU2A"
        ["title"]=>
        string(68) "Full-Duplex, Interference-Resilient and Harmonic-Rejection Receivers"
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(14) "Renaldi Winoto"
        ["chair2"]=>
        string(12) "Raja Pullela"
        ["chair_org"]=>
        string(27) "Marvell Semiconductor, Inc."
        ["chair_org2"]=>
        string(15) "MaxLinear, Inc."
        ["sessionId"]=>
        string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(418) "Modern communication systems require a wide dynamic range to co-exist with interferers, both self generated and from other sources in the environment. In this session, system and circuit techniques for interference cancellation, harmonic rejection and narrow-band notching are presented. The techniques presented here improve immunity to blockers and thus enable next generation systems, such as full-duplex receivers."
        ["child_sessions"]=>
        array(5) {
          ["TU2A-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2A"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(109) "Low Power Wideband Receiver With RF Self-Interference Cancellation for Full-Duplex and FDD Wireless Diversity"
            ["authors"]=>
            string(80) "Ehsan Kargaran, Saheed Tijani, Giacomo Pini, Danilo Manstretta, Rinaldo Castello"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(454) "Saw-Less Frequency Division Duplexing and Full-Duplex transceivers require very high receiver linearity. Self-Interference Cancellation can relax the specification but results in very high power. We propose a low-power direct-conversion single-ended receiver with passive SIC. A 28 nm CMOS prototype achieves an effective IIP3 > 25 dBm for both IB and OOB SI with only 20 dB cancellation and 25 dB isolation. Power consumption is 25 mW and area is 1 mm2."
            ["sessionId"]=>
            string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-1"
            ["presenter"]=>
            string(13) "Saheed Tijani"
            ["presenter_org"]=>
            string(14) "Univ. of Pavia"
            ["presenter_country"]=>
            string(5) "Italy"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2A-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2A"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(115) "An FD/FDD Transceiver With RX Band Thermal, Quantization,and Phase Noise Rejection and >64dB TX Signal Cancellation"
            ["authors"]=>
            string(67) "Sameet Ramakrishnan, Lucas Calderin, Ali Niknejad, Borivoje Nikolic"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(785) "A transceiver system with active cancellation of the TX signal for full duplex (FD) or frequency division duplex systems (FDD) is presented. A replica cancellation digital-to-analog converter and highly linear receiver with +25dBm OOB IIP3 enable FDD operation without a duplexer at TX power up to +17dBm, FD operation without a circulator up to +5dBm, and FD operation with a circulator up to +13dBm.  In addition to providing over 64dB of RF cancellation for a 20MHz modulated TX signal, the front-end demonstrates techniques to cancel noise sources in the RX band, including >2dB reduction of the thermal noise from the self-interference cancellation circuits, >25dB cancellation of quantization noise from the digital TX, and >20dB cancellation of TX LO phase noise in the RX band."
            ["sessionId"]=>
            string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-2"
            ["presenter"]=>
            string(14) "Lucas Calderin"
            ["presenter_org"]=>
            string(29) "Univ. of California, Berkeley"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2A-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2A"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(81) "A CMOS UWB Receiver With Reconfigurable Notch Filters for Narrow-Band Interferers"
            ["authors"]=>
            string(32) "Paria Sepidband, Kamran Entesari"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(833) "In this paper, an interferer-tolerant receiver for the first group of ultra-wideband systems (3.1-4.8 GHz) is presented. The entire system operates in two modes; detecting and receiving. In the detecting mode the interferers pass through a phaser-based interferer detector, which detects their frequency locations and reports the locations of up to three blockers in 2.35-2.75 GHz and 5.1-5.9 GHz bands to three notch filters used in the receiving path for rejection. In the receiving mode the signal passes through an LNA, the notch filters, a mixer, and a baseband filter. The entire system is integrated in a standard TSMC CMOS 65-nm technology and consumes up to 23.8 mW and 9.6 mW, in the receiving and detecting path, respectively, with a 1 V voltage supply. The receiver can achieve an out-of-band IIP3 of as high as 18.9 dBm."
            ["sessionId"]=>
            string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-3"
            ["presenter"]=>
            string(15) "Paria Sepidband"
            ["presenter_org"]=>
            string(15) "Texas A&M Univ."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2A-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2A"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(128) "A Full-Duplex Receiver With 80MHz Bandwidth Self-Interference Cancellation Circuit Using Baseband Hilbert Transform Equalization"
            ["authors"]=>
            string(125) "Ahmed El Sayed, Abdelrahman Ahmed, Amit Mishra, Amir Masnadi, Sang-Pil Woo, Yang-Seok Choi, Shahriar Mirabbasi, Sudip Shekhar"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(983) "To enable simultaneous full-duplex radios, self-interference cancellation (SIC) circuits that attain large cancellation bandwidth (BW) to support modern standards are needed. SIC must be implemented at the RF front-end in a linear, tunable, fully monolithic, and compact form factor. Emulating the group delay (GD) and complex impedance of the SI channel, an SIC circuit is proposed that achieves an 80 MHz of SIC BW. GD is estimated using frequency translations and baseband (BB) LPF, and complex impedance is emulated using a vector modulator (VM). We prove that combining the GD and VM results in a time-domain Hilbert transform equalization (HTE), enabling broadband cancellation and reducing SIC filter taps needed. Implementing HTE at BB using passive circuits further reduces area, power consumption and maintains linearity. A prototype in 0.13μm CMOS attains 23dB of SIC, while consuming 13mW in and 0.4mm2. Total power and area including the receiver are 64.4mW and 0.72mm2"
            ["sessionId"]=>
            string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-4"
            ["presenter"]=>
            string(14) "Ahmed El Sayed"
            ["presenter_org"]=>
            string(25) "Univ. of British Columbia"
            ["presenter_country"]=>
            string(6) "Canada"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2A-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2A"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(73) "A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion"
            ["authors"]=>
            string(55) "Heechai Kang, Wei-Gi Ho, Vineet Singh, Ranjit Gharpurey"
            ["location"]=>
            string(3) "312"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(512) "A wideband receiver employing single-stage harmonic-rejection mixers (HRM) is demonstrated. The HRM employs a 3-level PWM representation of a sinusoidal LO in combination with gain-ratios. The PWM LO signal is also used to perform gain control. The peak receiver gain with harmonic rejection is 31.8 dB, with a DSB NF of 5.8 dB. The design demonstrates worst-case HR3/HR5 ratios of 47 and 49 dB without any calibration for fLO=100 MHz and 3.7 dB PWM-based gain control, with a total power dissipation of 41.1 mW."
            ["sessionId"]=>
            string(38) "ead07018-87be-4d34-a521-063cc1b3f91c-5"
            ["presenter"]=>
            string(12) "Heechai Kang"
            ["presenter_org"]=>
            string(24) "Univ. of Texas at Austin"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496743200)
        ["stop_time_num"]=>
        int(1496749200)
      }
      [1]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU2B"
        ["title"]=>
        string(45) "System-on-Chip for Millimeter-Wave and Above "
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(13) "Vito Giannini"
        ["chair2"]=>
        string(11) "Tim LaRocca"
        ["chair_org"]=>
        string(10) "UHNDER Inc"
        ["chair_org2"]=>
        string(34) "Northrop Grumman Aerospace Systems"
        ["sessionId"]=>
        string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(488) "This session will focus on highly-integrated System-on-Chip solutions for sensing and communication applications at millimeter-wave and sub-millimeter-wave frequencies.  The papers demonstrate state-of-the-art performance using integrated on-chip antennas, multi-channel beamforming networks, and/or advanced transceiver architectures. These solutions may enable next-generation MIMO radar, ultra-high resolution imaging and wireless point-to-point bandwidth efficient QAM backhaul radio."
        ["child_sessions"]=>
        array(5) {
          ["TU2B-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2B"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(86) "Highly-Miniaturized 2-Channel mm-Wave Radar Sensor With On-Chip Folded Dipole Antennas"
            ["authors"]=>
            string(71) "Herman Ng, Wael Ahmad, Maciej Kucharski, Jeng-Hau Lu, Dietmar Kissinger"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(1024) "This paper describes a miniaturized 2-channel system-on-chip radar sensor in a SiGe BiCMOS technology. It includes on-chip folded dipole antennas that utilize a localized backside etching technique with a novel selective etching approach that is able to improve the radiation efficiency and the mechanical stability of the chip. The transceiver is equipped with a 30-GHz VCO that is complemented with a frequency quadrupler to generate a 120-GHz carrier signal. The 2 transmit channels can be combined to increase the effective isotropic radiated power by 6dB and to implement a SIMO radar. The transceiver also includes BPSK modulators as well as I/Q receivers and can be utilized to build a flexible MIMO radar using frequency-modulated continuous-wave with time and delta-sigma modulator-based frequency division multiplexing as well as pseudo-random noise radar techniques. Radar measurement using digital-beamforming method with 10-GHz modulation bandwidth was performed to show the applicabilty of the proposed system."
            ["sessionId"]=>
            string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-1"
            ["presenter"]=>
            string(9) "Herman Ng"
            ["presenter_org"]=>
            string(20) "IHP Microelectronics"
            ["presenter_country"]=>
            string(7) "Germany"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2B-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2B"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(118) "Fully-Scalable 2D THz Radiating Array: A 42-Element Source in 130-nm SiGe With 80-μW Total Radiated Power at 1.01 THz"
            ["authors"]=>
            string(18) "Zhi Hu, Ruonan Han"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(608) "This paper presents a 1-THz radiating array using IHP 130-nm SiGe process. It is based on a highly-scalable 2D structure that uses a square grid of slots to simultaneously (1) maximize and synchronize the fundamental oscillation (f0=250 GHz) and 4th-harmonic generation (4f0=1 THz) of a large array of transistors, (2) synthesize standing-wave patterns with near-field cancellation at f0, 2f0 and 3f0 and efficient radiation at 4f0. The compact design enables implementation of 42 coherent radiators on a 1mm2 area. The chip consumes 1.1-W DC power and generates 80-μW total radiated power with 13-dBm EIRP."
            ["sessionId"]=>
            string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-2"
            ["presenter"]=>
            string(6) "Zhi Hu"
            ["presenter_org"]=>
            string(37) "Massachusetts Institute of Technology"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2B-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2B"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(106) "A Wideband SiGe BiCMOS Transceiver Chip-set for High-Performance Microwave Links in the 5.6-43.5 GHz Range"
            ["authors"]=>
            string(140) "Yves Baeyens, Shahriar Shahramian, Bahar Jalali_Farahani, Pascal Roux, Joe Weiner, Amit Singh, Maurizio Moretto, Pascal Boutet, Pierre Lopez"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(484) "In this paper, we present a chip-set of 4 wideband SiGe BiCMOS transceivers optimized for the stringent specifications of various microwave links in the 5-44 GHz range. Each receiver and transmitter covers full frequency bands of 5.6-8.5 GHz, 10-15.5 GHz, 17.5-26.5 GHz and 27-43.5 GHz and demonstrates high dynamic range and excellent noise figure and linearity. Radio links demonstrate error-free operation for channel bandwidths from 7 up to 112 MHz and modulations up to 4096 QAM."
            ["sessionId"]=>
            string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-3"
            ["presenter"]=>
            string(12) "Yves Baeyens"
            ["presenter_org"]=>
            string(17) "Nokia / Bell-Labs"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2B-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2B"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(73) "A Fully-Integrated 94-GHz 32-Element Phased-Array Receiver in SiGe BiCMOS"
            ["authors"]=>
            string(137) "Jean-Olivier Plouchart, Wooram Lee, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Emre Apaydin, Alberto Valdes-Garcia"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(765) "A 94GHz phased array receiver IC in 130nm BiCMOS technology is reported. The design integrates 32 front ends with gain and phase control configurable using look-up table memory, two separate 16:1 power combiner trees, two 94GHz to ~10GHz (IF) down conversion mixers, an IF to baseband (BB) quadrature down conversion mixer, and a 42GHz PLL followed by a frequency doubler implementing the LO source. The IC occupies an area of 6.7mmX5.6mm and can either support a 32-element phased array or a 16-element polarimetric phased array. In on-wafer measurements at 94GHz and 25C, the design achieves maximum RF to IF array conversion gain of 41dB, maximum RF to BB array conversion gain of 69dB, 20dB of RF front-end gain programmability, NF of 6 dB, and RMS phase error "
            ["sessionId"]=>
            string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-4"
            ["presenter"]=>
            string(22) "Jean-Olivier Plouchart"
            ["presenter_org"]=>
            string(31) "IBM T.J. Watson Research Center"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2B-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2B"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(66) "A 71-86 GHz Bidirectional Image Selection Transceiver Architecture"
            ["authors"]=>
            string(32) "Najme Ebrahimi, James Buckwalter"
            ["location"]=>
            string(4) "313A"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(764) "A bidirectional image selection transceiver is presented that operates over 71-76 GHz and 81-86 GHz with only 3 GHz of LO tuning range. A sliding-IF architecture with bidirectional VGAs allows operation in transmit and receive modes. The sliding IF and narrow LO tuning range allow wideband image rejection using a single stage polyphase filter. The circuit is implemented in a 90-nm SiGe BiCMOS process. Measurements indicate conversion gain of -2.5 dB to 3 dB with less than ±0.75 dB variation over 10 GHz in TX mode and -4dB to 0 dB with less than ±1 dB variation over 10 GHz bandwidth in RX mode. With 16- and 64-QAM, the EVM is below 5% and 4% at data rates of 6 Gb/s and 9 Gb/s. The RF signal path consumes at most 150 mW while the LO path consumes 250 mW."
            ["sessionId"]=>
            string(38) "6ede0da8-5b02-488c-9e2e-2fbc8a3fe317-5"
            ["presenter"]=>
            string(14) "Najme Ebrahimi"
            ["presenter_org"]=>
            string(32) "Univ. of California at San Diego"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496743200)
        ["stop_time_num"]=>
        int(1496749200)
      }
      [2]=>
      array(14) {
        ["subcom"]=>
        string(4) "TU2D"
        ["title"]=>
        string(42) "Power Amplifiers in Advanced Technologies "
        ["date"]=>
        string(20) "Tuesday, 6 June 2017"
        ["chair"]=>
        string(20) "Margaret Szymanowski"
        ["chair2"]=>
        string(10) "Nick Cheng"
        ["chair_org"]=>
        string(18) "NXP Semiconductors"
        ["chair_org2"]=>
        string(18) "Skyworks Solutions"
        ["sessionId"]=>
        string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-1"
        ["organizer"]=>
        string(0) ""
        ["organizer_org"]=>
        string(0) ""
        ["abstract"]=>
        string(145) "This session presents PA designs in cutting edge technologies, including GaN, GaAs, SiGe, SOI and FinFET CMOS, to address 5G and mm-wave systems."
        ["child_sessions"]=>
        array(5) {
          ["TU2D-1"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2D"
            ["sequence"]=>
            string(1) "1"
            ["paper_title"]=>
            string(50) "Peaking PA Bias Circuit for an APT CMOS Doherty PA"
            ["authors"]=>
            string(75) "Joonhoi Hur, Paul Draxler, Joung Won Park, Anthony Segoria, Vladimir Aparin"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(701) "This paper presents a peaking PA bias circuit for an Average Power Tracking (APT) CMOS Doherty PA, where the common supply voltage changes as the target average power changes. In order to have Doherty efficiency characteristics with APT, the adaptive bias circuit shifts the bias of the peaking PA as the supply voltage changes, activating the peaking PA at the correct backoff (6dB) from the Posat for that supply voltage. This bias circuit is demonstrated on a CMOS Doherty PA using standard 0.18um SOI. With the proposed bias circuit, the Doherty PA has specification compliant WCDMA performance (with DPD) up to 29dBm Pout, with 40-50% PAE (from 25-29dBm Pout) and supply voltages from 1.5V to 4V."
            ["sessionId"]=>
            string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-1"
            ["presenter"]=>
            string(11) "Joonhoi Hur"
            ["presenter_org"]=>
            string(27) "Qualcomm Technologies, Inc."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2D-2"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2D"
            ["sequence"]=>
            string(1) "2"
            ["paper_title"]=>
            string(97) "An X-Band Inverse Class-F SiGe HBT Cascode Power Amplifier With Harmonic-Tuned Output Transformer"
            ["authors"]=>
            string(24) "Inchan Ju, John Cressler"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(896) "This paper presents a highly efficient X-band inverse class-F SiGe HBT cascode power amplifier (PA) to overcome performance limitations imposed by device breakdown. Simultaneous fundamental and 2nd/3rd harmonic matching is achieved using an output transformer with an embedded capacitor at its center-tap, which enables inverse class-F operation. Use of a cascode topology with a low base impedance termination and minimum voltage-current waveform overlap extends the voltage swing of PA beyond BVCBO, boosting output power and power added efficiency (PAE). As proof of concept, the inverse class-F PA was implemented in 0.13-μm SiGe BiCMOS technology. Measured results show an output power of 25.8 dBm and 51.1% peak PAE at 10 GHz, when operated on a 3.0 V supply. To the authors’ best knowledge, our work has the highest efficiency among all Si-based X-band PAs with comparable output power."
            ["sessionId"]=>
            string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-2"
            ["presenter"]=>
            string(9) "Inchan Ju"
            ["presenter_org"]=>
            string(31) "Georgia Institute of Technology"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2D-3"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2D"
            ["sequence"]=>
            string(1) "3"
            ["paper_title"]=>
            string(106) "A 6−18 GHz GaN Distributed Power Amplifier Using Reactive Matching Technique and Simplified Bias Network"
            ["authors"]=>
            string(136) "Hongjong Park, Sangho Lee, Kwangseok Choi, Jihoon Kim, Hyosung Nam, Jaeduk Kim, Wangyong Lee, Changhoon Lee, Junghyun Kim, Youngwoo Kwon"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(848) "Two-stage reactively matched gain cells are applied to design a high-gain multi-octave distributed power amplifier (DPA) in this paper. The proposed reactively matched distributed amplifier (RMDA) structure shows a high gain and high output power performance within a small die size. The DC bias network of each section is simplified to implement the proposed structure in an MMIC and the design guide for the bias network is provided. A 6–18 GHz GaN DPA fabricated with the commercial 0.25-μm GaN HEMT process shows output power reaching 40.3–43.9 dBm with 16–27% PAE. To the best of our knowledge, this is the first demonstration of a GaN DPA using reactively matched gain cells, and it exhibits excellent small-signal gain and RF power performance capabilities among other reported GaN PAs with a multi-octave bandwidth up to the Ku-band."
            ["sessionId"]=>
            string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-3"
            ["presenter"]=>
            string(13) "Hongjong Park"
            ["presenter_org"]=>
            string(20) "Seoul National Univ."
            ["presenter_country"]=>
            string(18) "Korea, Republic of"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2D-4"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2D"
            ["sequence"]=>
            string(1) "4"
            ["paper_title"]=>
            string(63) "A Ka-Band Asymmetrical Stacked-FET MMIC Doherty Power Amplifier"
            ["authors"]=>
            string(35) "Duy Nguyen, Thanh Pham, Anh-Vu Pham"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(736) "We present a stacked-FET monolithic millimeter-wave (mmW) integrated circuit Doherty power amplifier (DPA). The DPA employs a novel asymmetrical stack gate bias to achieve high power and high efficiency at 6-dB power back-off (PBO). The circuit is fabricated in a 0.15-μm enhancement mode (E-mode) Gallium Arsenide (GaAs) process.  Experimental results demonstrate output power at 1-dB gain compression (P1dB) of 28.2 dBm, peak power added efficiency (PAE) of 37% and PAE at 6-dB PBO of 27% at 28 GHz.  Measured small signal gain is 15 dB while the 3-dB bandwidth covers from 25.5 to 29.5 GHz. Using digital predistortion (DPD) with a 20 MHz 64 QAM modulated signal, an adjacent channel power ratio (ACPR) of -46 dBc has been observed."
            ["sessionId"]=>
            string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-4"
            ["presenter"]=>
            string(10) "Duy Nguyen"
            ["presenter_org"]=>
            string(26) "Univ. of California, Davis"
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
          ["TU2D-5"]=>
          array(23) {
            ["subcom"]=>
            string(4) "TU2D"
            ["sequence"]=>
            string(1) "5"
            ["paper_title"]=>
            string(51) "A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS"
            ["authors"]=>
            string(53) "Steven Callender, Stefano Pellerano, Christopher Hull"
            ["location"]=>
            string(4) "313B"
            ["mode"]=>
            string(0) ""
            ["length"]=>
            string(1) "0"
            ["start"]=>
            string(4) "1000"
            ["stop"]=>
            string(4) "1140"
            ["date"]=>
            string(20) "Tuesday, 6 June 2017"
            ["paper_link"]=>
            string(0) ""
            ["updated"]=>
            string(10) "1491494417"
            ["abstract"]=>
            string(550) "This paper presents the design of an E-Band PA in Intel 14nm FinFET/trigate CMOS process. Device layout optimizations are used to maximize device performance at mm-wave frequencies and overcome the impact of scaling on RF performance. Neutralization and low-k transformer-based matching networks are employed to improve gain and bandwidth.  The PA achieves a peak gain of 11.9dB/16.7 dB at 71GHz with a bandwidth of 8.5GHz/7.4 GHz in low-gain/high-gain mode. At 71GHz, the measured Psat, OP1dB and peak PAE are 7.3dBm, 1.6dBm, and 8.3%, respectively."
            ["sessionId"]=>
            string(38) "25a74049-2e95-463c-8971-5300dbf32cdf-5"
            ["presenter"]=>
            string(16) "Steven Callender"
            ["presenter_org"]=>
            string(11) "Intel Corp."
            ["presenter_country"]=>
            string(13) "United States"
            ["start_time_num"]=>
            int(1496743200)
            ["start_h"]=>
            string(2) "10"
            ["start_m"]=>
            string(2) "00"
            ["stop_time_num"]=>
            int(1496749200)
            ["stop_h"]=>
            string(2) "11"
            ["stop_m"]=>
            string(2) "40"
          }
        }
        ["start_time_num"]=>
        int(1496743200)
        ["stop_time_num"]=>
        int(1496749200)
      }
    }
    ["11:45 - 12:45"]=>
    array(1) {
      [0]=>
      array(16) {
        ["subcom"]=>
        string(1) "2"
        ["title"]=>
        string(39) "Who Wants to be a Millimeterwavionaire?"
        ["date"]=>
        NULL
        ["chair"]=>
        string(0) ""
        ["chair2"]=>
        string(0) ""
        ["chair_org"]=>
        string(0) ""
        ["chair_org2"]=>
        string(0) ""
        ["sessionId"]=>
        string(36) "35f161a9-a3e8-4e1a-b2a5-0441e4c7da1c"
        ["organizer"]=>
        string(56) "Earl McCune, Sherry Hess, Bodhisatwa Sadhu, Oren Eliezer"
        ["organizer_org"]=>
        string(53) "Eridan Communicatinos, AWR Corp., IBM Research, PHAZR"
        ["abstract"]=>
        string(582) "Two teams of contestants, including preselected and randomly selected contestants from the audience, will compete in answering questions on RF and microwave theory and history, including IMS/RFIC conference trivia.  Prizes will be awarded to the contestants, as well as to others in the audience who may be called upon for answers.  Bring your lunch and be prepared for a great deal of entertainment and a little bit of learning too!

Contestants:    
You’ll find out when you get there!   Maybe you will be one of them?" ["start_time_num"]=> int(1496749500) ["stop_time_num"]=> int(1496753100) ["color"]=> string(6) "4b80d6" ["color_id"]=> string(1) "9" ["color_name"]=> string(17) "Panel Discussions" } } } }
Sun. 4 June
19:30 - 9:30
100:
Interactive Forum
Chair: 
Waleed Khalil
Chair organization: 
Ohio State Univ.
Co-chair: 
Jennifer Kitchen
Co-chair organization: 
Arizona State Univ.
Presentations in this session
100-1 : A Wideband Receiver With +32.5dBm Effective OB-IIP3 Using IM3 Cancellation in the Baseband
Authors:
Yudong Zhang, Jianxun Zhu, Peter Kinget
Presenter:
Yudong Zhang, Columbia Univ., United States
100-2 : Envelope Time-Domain Characterizations to Asses In-Band Linearity Performances of Pre-Matched MASMOS Power Amplifier
Authors:
Frédérique Simbélie, Sylvain Laurent, Pierre Medrel, Yann Creveuil, Myrianne Regis, Michel Prigent, Raymond Quéré
Presenter:
Frédérique Simbélie, Xlim - CNRS- Unversite De Liroges, France
100-3 : Improving the Linearity of Wideband Receiver Systems by Component IM3 Phasor Manipulation
Authors:
Gabor Varga, Fabian Speicher, Arun Ashok, Iyappan Subbiah, Moritz Schrey, Ralf Wunderlich, Stefan Heinen
Presenter:
Stefan Heinen, RWTH Aachen Univ., Germany
100-4 : A Fully-Integrated SOI CMOS Complex-Impedance Detector forMatching Network Tuning in LTE Power Amplifier
Authors:
Dominique Nicolas, Ayssar Serhan, Alexandre Giry, Thierry Parra, Éric Mercier
Presenter:
Ayssar Serhan, CEA-LETI Minatec, France
100-5 : V-Band Flip-Chip pHEMT Balanced Power Amplifier With CPWG-MS-CPWG Topology and CPWG Lange Couplers
Authors:
Wei-Ling Chang, Jen-Yi Su, Chinchun Meng, Chia-Hung Chang, Guo-Wei Huang
Presenter:
Wei-Ling Chang, National Chiao Tung Univ., Taiwan
100-6 : Multi-Standard 5 Gbps to 28.2 Gbps Adaptive, Single Voltage SerDes Transceiver With Analog FIR and 2-tap Unrolled DFE in 28 nm CMOS
Authors:
Mohammad Mahani, Rod Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, Peter Graumann, Hans Ransijn, Tomas Dusatko, Stanley Ho, Phillip Snyder, Jomy Joy, Suresh Nalluri, Tony Zortea
Presenter:
Mohammad Mahani, Microsemi Corp., Canada
100-7 : A Harmonic-Selective Wireless Full-Band-Capture Receiver With Digital Harmonic Rejection Calibration
Authors:
Hao Wu, David Murphy, Hooman Darabi
Presenter:
Hao Wu, Broadcom Corp., United States
100-8 : A 40GHz PLL With -92.5dBc/Hz In-Band Phase Noise and 104fs-RMS-Jitter
Authors:
Ying Chen, Louis Praamsma, Nikola Ivanisevic, Domine Leenaerts
Presenter:
Ying Chen, NXP Semiconductors, United States
100-9 : A High-Efficiency Linear Power Amplifier for 28GHz Mobile Communications in 40nm CMOS
Authors:
Yang Zhang, Patrick Reynaert
Presenter:
Yang Zhang, KU Leuven, Belgium
100-10 : An Analysis of Phase Noise Requirements for Ultra-Low-Power FSK Radios
Authors:
Xing Chen, Hun-Seok Kim, David Wentzloff
Presenter:
Xing Chen, Univ. of Michigan, United States
100-11 : A Ka-Band 4-ch Bi-Directional CMOS T/R Chipset for 5G Beamforming System
Authors:
JangHoon Han, JinHyun Kim, JeongSoo Park, JeongGeun Kim
Presenter:
JangHoon Han, Kwangwoon Univ., Korea, Republic of
100-12 : A 32 GHz 20 dBm-Psat Transformer-Based Doherty Power Amplifier for Multi-Gb/s 5G Applications in 28 nm Bulk CMOS
Authors:
Paramartha Indirayanti, Patrick Reynaert
Presenter:
Paramartha Indirayanti, Katholieke Univ. Leuven, Belgium
100-13 : A 10-40 GHz Frequency Quadrupler Source With Switchable Bandpass Filters and >30 dBc Harmonic Rejection
Authors:
Hyunchul Chung, Qian Ma, Gabriel Rebeiz
Presenter:
Hyunchul Chung, Univ. of California at San Diego, United States
100-14 : Joint TX and Feedback RX IQ Mismatch Compensation for Integrated Direct Conversion Transmitters
Authors:
Hunsoo Choo, Charles Sestok, Xiaoxi Zhang, Nikolaus Klemmer
Presenter:
Hunsoo Choo, Texas Instruments, Inc., United States
100-15 : A Precision 140MHz Relaxation Oscillator in 40nm CMOS With 28ppm/ºC Frequency Stability for Automotive SoC Applications
Authors:
Dmytro Cherniak, Roberto Nonis, Fabio Padovan
Presenter:
Fabio Padovan, Infineon Technologies AG, Austria
Mon. 5 June
8:00 - 9:40
MO1A:
28GHz Phased-Array Transceivers for 5G systems
Chair: 
Stefano Pellerano
Chair organization: 
Intel Corp.
Co-chair: 
Hossein Hashemi
Co-chair organization: 
Univ. of Southern California
Location: 
312
Abstract: 
This sessions presents the latest advancements in 28GHz Phased-Array transceivers targeted for 5G systems. In the firs paper, a two-channel bi-directional phased-array chip for the construction of high-power, high-linearity base stations is presented. The second paper presents a four-element transceiver with scalar-only weighting functions and dual-vector series feed network. In the third paper, a direct-conversion transceiver with packaged 2x4 patch antenna arrays is presented. Finally, the last paper demonstrate a low-cost 32-element phased-array architecture with 8 2x2 transceiver core chips integrated on PCB with antennas and combiners.
Presentations in this session
MO1A-1 : Bi-Directional Flip-Chip 28 GHz Phased-Array Core-Chip in 45nm CMOS SOI for High-Efficiency High-Linearity 5G Systems
Authors:
Umut Kodak, Gabriel Rebeiz
Presenter:
Umut Kodak, Univ. of California at San Diego, United States
MO1A-2 : A 28-GHz Phased-Array Transceiver with Series-Fed Dual-Vector Distributed Beamforming
Authors:
Yi-Shin Yeh, Ed Balboni, Brian Floyd
Presenter:
Yi-Shin Yeh, North Carolina State Univ., United States
MO1A-3 : A 28GHz CMOS Direct Conversion Transceiver With Packaged Antenna Arrays for 5G Cellular System
Authors:
Hong Teuk Kim, Byoung Sun Park, Seung Min Oh, Seong Sik Song, Jong Moon Kim, So Hyeong Kim, Tak Su Moon
Presenter:
Hong Teuk Kim, LG Electronics, Korea, Republic of
MO1A-4 : An Ultra Low-Cost 32-Element 28 GHz Phasedm EIRP and 1.0-1.6 Gbps 16-QAM Link at 300 Meters-Array Transceiver With 41 dB
Authors:
Kerim Kibaroglu, Mustafa Sayginer, Gabriel Rebeiz
Presenter:
Kerim Kibaroglu, Univ. of California at San Diego, United States
MO1B:
Advanced Technologies for Optical, Millimeter Wave and Radio Frequency Applications
Chair: 
Freek van Straten
Chair organization: 
Ampleon
Co-chair: 
Richard Chan
Co-chair organization: 
QORVO, Inc.
Location: 
313A
Abstract: 
Advances in specific applications for sub-THz signal generation using optical sources, advanced RFCMOS with excellent leakage performance and State-of-the-art pFET switching speed, compact low-cost quad-band filter topology and broadband power detection technique are reported.
Presentations in this session
MO1B-1 : Sub-THz Source Integrated in Low-Cost Silicon Photonic Technology Targeting 40 Gb/s Wireless Links
Authors:
Elsa Lacombe, Frederic Gianesello, Cedric Durand, Guillaume Ducournau, Cyril Luxey, Daniel Gloria
Presenter:
Frederic Gianesello, STMicroelectronics, France
MO1B-2 : RF NMOS Switch With Dedicated Sinks for Reduced Leakage Current
Authors:
Mahmoud S. M. Al-Sa'di, Johan J. T. M. Donkers, Peter H. C. Magnée, Ihor Brunets, Jan W. Slotboom
Presenter:
Mahmoud S. M. Al-Sa'di, NXP Semiconductors, The Netherlands
MO1B-3 : RF-pFET in Fully Depleted SOI Demonstrates 420 GHz FT
Authors:
Josef Watts, Kumaran Sundaram, Kok Wai Chew, Shih Ni Ong, Steffen Lehmann, Wai Heng Chow, Lye Hock Kelvin Chan, Jerome Mazurier, Christoph Schwan, Yogadissen Andee, Thomas Feudel, Luca Pirro, Elke Erben, Edward Nowak, Elliot Smith, El Mehdi BAZIZI, Thorsten Kammler, Richard Taylor III, Bryan Rice, David Harame
Presenter:
Josef Watts, GLOBALFOUNDRIES, United States
MO1B-4 : Validation of a Functional Principle for a Broadband Millimeter-Wave Power Detection Structure in a Recent BiCMOS Technology
Authors:
Florian Trenz, Robert Weigel, Dietmar Kissinger
Presenter:
Florian Trenz, Univ. of Erlangen-Nuremberg, Germany
MO1D:
High-Performance Frequency Synthesizers
Chair: 
Jeyanandh Paramesh
Chair organization: 
Carnegie Mellon Univ.
Co-chair: 
Jaber Khoja
Co-chair organization: 
Rockwell Collins, Inc.
Location: 
313B
Abstract: 
The session deals with high-frequency generation schemes for different applications as automotive radars, rotational spectroscopy and clock generation for digital systems. A beyond-state-of-the-art digital PLL for an LTE-A polar transmitter and an inductor-less sub-sampling fractional-N PLL will be also presented.
Presentations in this session
MO1D-1 : A 59-to-276 GHz CMOS Signal Generation for Rotational Spectroscopy
Authors:
Xiaolong Liu, Yue Chao, Howard Luong
Presenter:
Xiaolong Liu, Hong Kong Univ. of Science and Technology, Hong Kong
MO1D-2 : A Fully Integrated 75-83 GHz FMCW Synthesizer for Automotive Radar Applications With -97 dBc/Hz Phase Noise at 1 MHz Offset and 100 GHz/mSec Maximal Chirp Rate
Authors:
Jakob Vovnoboy, Run Levinger, Nadav Mazor, Danny Elad
Presenter:
Jakob Vovnoboy, ON Semiconductor, Israel
MO1D-3 : A Subharmonically Injection-Locked PLL With 130 fs RMS Jitter at 24 GHz Using Synchronous Reference Pulse Injection From Nonlinear VCO Envelope Feedback
Authors:
Dongseok Shin, Shinwoong Park, Sanjay Raman, Kwang-Jin Koh
Presenter:
Dongseok Shin, Virginia Polytechnic Institute and State Univ., United States
MO1D-4 : A Highly Reconfigurable RF-DPLL Phase Modulator for Polar Transmitters in Multi-Band/Multi-Standard Cellular RFICs
Authors:
Tobias Buckel, Thomas Mayer, Thomas Bauernfeind, Stefan Tertinek, Christian Wicpalek, Andreas Springer, Robert Weigel, Thomas Ussmueller
Presenter:
Tobias Buckel, Danube Mobile Communications Engineering, Austria
MO1D-5 : A Low-Noise Inductor-Less Fractional-N Sub-Sampling PLL With Multi-Ring Oscillator
Authors:
Dongyi Liao, Ruixin Wang, Fa Dai
Presenter:
Dongyi Liao, Auburn Univ., United States
10:00 - 11:40
MO2A:
Radio Building Blocks for 5G Systems
Chair: 
Walid Ali-Ahmad
Chair organization: 
Qualcomm, Inc.
Co-chair: 
Bodhisatwa Sadhu
Co-chair organization: 
IBM T.J. Watson Research Center
Location: 
312
Abstract: 
This session presents key building blocks for radio transceivers targeted for 5G systems. The first paper describes an 8-element, 2-stream hybrid beamforming receiver for MIMO communication operating at 25-30GHz. In the second paper, a wideband 29-to-57GHz power amplifier with AM-PM compensation for 5G phased-arrays is presented. In the last two papers, two digital beamforming solutions are described: a quad-channel, 1GS/s collaborative ADC for a four-channel MIMO receiver and a 16-element, 4-beam digital beam-former combining continuous-time band-pass delta sigma modulators with interleaved bit-stream processing.
Presentations in this session
MO2A-1 : A 25-30 GHz 8-Antenna 2-Stream Hybrid Beamforming Receiver for MIMO Communication
Authors:
Susnata Mondal, Rahul Singh, Ahmed Hussein, Jeyanandh Paramesh
Presenter:
Susnata Mondal, Carnegie Mellon Univ., United States
MO2A-2 : A 29-to-57GHz AM-PM Compensated Class-AB Power Amplifier for 5G Phased Arrays in 0.9V 28nm Bulk CMOS
Authors:
Marco Vigilante, Patrick Reynaert
Presenter:
Marco Vigilante, Katholieke Univ. Leuven, Belgium
MO2A-3 : A Quad Channel 11-bit 1 GS/s 39.56 mW Collaborative ADC Based Digital Beamforming for 5G Wireless.
Authors:
Aurangozeb, Farshid Aryanfar, Masum Hossain
Presenter:
Aurangozeb, Univ. of Alberta, Canada
MO2A-4 : A 16-Element 4-Beam 1GHz-IF 100MHz-Bandwidth Interleaved Bit Stream Digital Beamformer in 40nm CMOS
Authors:
Sunmin Jang, Jaehun Jeong, Rundao Lu, Michael Flynn
Presenter:
Sunmin Jang, Univ. of Michigan, United States
MO2B:
Modeling and Characterization for Emerging High Frequency and RF Front-end Applications
Chair: 
Tzung-Yin Lee
Chair organization: 
Skyworks Solutions
Co-chair: 
Edward Preisler
Co-chair organization: 
TowerJazz
Location: 
313A
Abstract: 
This session begins with modeling of RF switches for wireless front-end applications, followed by practical CMOS FET modeling for RF IC design, and test structure design optimization for very high-frequency characterization. Next, modeling of SMT devices, which are integral in today’s commercial front end modules, is presented. Finally, modeling of GaN HEMTs is discussed with an emphasis on large-signal vs. small-signal characteristics.
Presentations in this session
MO2B-1 : Accurate Modeling and Optimization of Inhomogeneous Substrate Related Losses in SPDT Switch IC Design for WLAN Applications
Authors:
Fadoua Gacim, Philippe Descamps
Presenter:
Fadoua Gacim, Normandie Université ENSICAEN, Unicaen, CRISMAT, France
MO2B-2 : A Simplified CMOS FET Model Using Surface Potential Equations For Inter-Modulation Simulations of Passive-Mixer-Like Circuits
Authors:
Mahmood Baraani Dastjerdi, Harish Krishnaswamy
Presenter:
Mahmood Baraani Dastjerdi, Columbia Univ., United States
MO2B-3 : Broadband Effect of Linear Tapered Transitions Between Probe Pads and GCPW Signal Lines On-Chip
Authors:
Tinus Stander
Presenter:
Tinus Stander, University of Pretoria, South Africa
MO2B-4 : Accurate EM Simulation of SMT Components in RF Designs
Authors:
Weimin Sun
Presenter:
Weimin Sun, Skyworks Solutions, United States
MO2B-5 : Variation of Intrinsic Components From Small-Signal Model of AlGaN/GaN HEMTs in Linear and Saturation Regions After Off-State Bias
Authors:
Yue-Ming Hsin, Yi-Nan Zhong, Zhen-Wei Liu
Presenter:
Yue-Ming Hsin, National Central Univ., Taiwan
MO2D:
mm-Wave and THz Sources
Chair: 
Mohyee Mikhemar
Chair organization: 
Broadcom Corp.
Co-chair: 
Ehsan Afshari
Co-chair organization: 
Univ. of Michigan
Location: 
313B
Abstract: 
Millimeter-wave and Terahertz systems have many applications in high data-rate communication, sensing, and spectroscopy. Recently there has been many works at this frequency range in silicon-based technologies. The papers in this session push the limit of mm-wave and THz sources in terms of power efficiency, phase noise, and output power.
Presentations in this session
MO2D-1 : An 8-Element Common-Mode-Coupled 106 GHz Fundamental Oscillator With -111 dBc/Hz Phase Noise at 1 MHz Offset
Authors:
Alireza Imani, Hossein Hashemi
Presenter:
Alireza Imani, Univ. of Southern California, United States
MO2D-2 : A 195 GHz Single-Transistor Fundamental VCO With 15.3% DC-to-RF Efficiency, 4.5 mW Output Power, Phase Noise FoM of -197 dBc/Hz and 1.1% Tuning Range in a 55 nm SiGe Process
Authors:
Hamid Khatibi, Somayeh Khiyabani, Andreia Cathelin, Ehsan Afshari
Presenter:
Ehsan Afshari, Univ. of Michigan, United States
MO2D-3 : Energy Efficient Distributed-Oscillators at 134 and 202GHz With Phase-Noise Optimization through Body-Bias Control in 28nm CMOS FDSOI Technology
Authors:
Raphael Guillaume, Francois Rivet, Andreia Cathelin, Yann Deval
Presenter:
Raphael Guillaume, STMicroelectronics, France
MO2D-4 : A Lens-Integrated 430 GHz SiGe HBT Source With Up to -6.3 dBm Radiated Power
Authors:
Philipp Hillger, Janusz Grzyb, Stefan Malz, Bernd Heinemann, Ullrich Pfeiffer
Presenter:
Philipp Hillger, University of Wuppertal, Germany
MO2D-5 : An Ultra-Wideband Harmonic Radiator With a Tuning Range of 62GHz (28.3%) at 220GHz
Authors:
Ali Mostajeran, Ehsan Afshari
Presenter:
Ali Mostajeran, Cornell Univ., United States
11:45 - 12:45
1:
5th Generation Wireless – Where is That Going and What’s in it for me?
Organizer: 
Oren Eliezer, Brian Floyd, Bodhisatwa Sadhu
Organizer organization: 
PHAZR, North Carolina State Univ., IBM Corp.
Abstract: 
A panel of 5 experts from the industry and academia will debate different challenges associated with the development and deployment of 5th generation wireless systems; when and how the advancements in technologies such as massive MIMO, beamforming, phased arrays, and millimeter wave ICs will allow such systems to reach their performance and cost targets; and, of course, how will all that impact us, the community of RF engineers and end users.
13:30 - 15:10
MO3A:
Ultra-Low Power Wake-up Receivers
Chair: 
David Wentzloff
Chair organization: 
Univ. of Michigan
Co-chair: 
Arun Natarajan
Co-chair organization: 
Oregon State Univ.
Location: 
312
Abstract: 
This session presents several novel ultra-low power wake-up receivers. The first three papers are compatible with Bluetooth Low-Energy and WiFi standards by detecting either back-channel messages, or designed for the proposed 802.11 wake-up protocol. A wake-up receiver is presented with the highest reported sensitivity for a sub-1uW receiver. Finally, an RF front-end is presented leveraging a current reuse technique to reduce power.
Presentations in this session
MO3A-1 : A 2.4GHz BLE-Compliant Fully-Integrated Wakeup Receiver for Latency-Critical IoT Applications Using a 2-Dimensional Wakeup Pattern in 90nm CMOS
Authors:
Ming Ding, Peng Zhang, Chuang Lu, Yan Zhang, Stefano Traferro, Gert-Jan van Schaik, Yao-Hong Liu, Jarkko Huijts, Christian Bachmann, guido dolmans, Kathleen Philips
Presenter:
Ming Ding, Holst Centre, The Netherlands
MO3A-2 : 95μW 802.11g/n Compliant Fully-Integrated Wake-Up Receiver With -72dBm Sensitivity in 14nm FinFET CMOS
Authors:
Erkan Alpman, Ahmad Khairi, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey Foerster, Ashoke Ravi, Stefano Pellerano
Presenter:
Erkan Alpman, Intel Corp., United States
MO3A-3 : A 335µW -72dBm Receiver for FSK Back-Channel Embedded in 5.8GHz Wi-Fi OFDM packets
Authors:
Jaeho Im, Hun-Seok Kim, David Wentzloff
Presenter:
Jaeho Im, Univ. of Michigan, United States
MO3A-4 : A 365nW -61.5dBm Sensitivity, 1.875cm^2 2.4GHz Wake-up Receiver With Rectifier-Antenna Co-Design for Passive Gain
Authors:
Kamala Raghavan Sadagopan, Jian Kang, Sanket Jain, Yogesh Ramadass, Arun Natarajan
Presenter:
Kamala Raghavan Sadagopan, Oregon State Univ., United States
MO3A-5 : A 64 uW, 23 dB Gain, 8 dB NF, 2.4 GHz RF Front-end for Ultra-Low Power Internet-of-Things Transceivers
Authors:
Anjana Dissanayake, Hyun-Gi Seok, Oh-Yong Jung, Sok-Kyun Han, Sang-Gug Lee
Presenter:
Anjana Dissanayake, Korea Advanced Institute of Science and Technology, Korea, Republic of
MO3B:
Next Generation Transmitters and Receivers for Cellular and Wireless Connectivity
Chair: 
Julian Tham
Chair organization: 
Cypress Semiconductor Corp.
Co-chair: 
Yuan-Hung Chung
Co-chair organization: 
MediaTek, Inc.
Location: 
313A
Abstract: 
This session covers next generation transmitter and receiver architectures for Cellular and Wireless Connectivity applications. Three papers present various digital techniques for transmitters. A cellular receiver design supporting 5CC carrier aggregation and a WiFi transceiver design with integrated power amplifiers for 160MHz 802.11ac are presented in two other papers.
Presentations in this session
MO3B-1 : A Wideband Linear Direct Digital RF Modulator Using Harmonic Rejection and I/Q-Interleaving RF DACs
Authors:
Mohammadreza Mehrpoo, Mohsen Hashemi, Yiyu Shen, Rene van Leuken, Morteza S. Alavi, Leo C. N. de Vreede
Presenter:
Mohammadreza Mehrpoo, Delft Univ. of Technology, The Netherlands
MO3B-2 : A Dual Core Power Combining Digital Power Amplifier for 802.11b/g/n with +26.8dBm Linear Output Power in 28nm CMOS
Authors:
Alden Wong, Philip Godoy, Ovidiu Carnu, Hao Li, Xingliang Zhao, Ashkan Olyaei, Amir Ghaffari, Sai-Wang Tam, Renaldi Winoto, Randy Tsang
Presenter:
Alden Wong, Marvell Semiconductor, Inc., United States
MO3B-3 : A Fully-Integrated Digital-Intensive Polar Doherty Transmitter
Authors:
Yiyu Shen, Mohammadreza Mehrpoo, Mohsen Hashemi, Michael Polushkin, Lei Zhou, Mustafa Acar, Rene van Leuken, Morteza Alavi, Leo de Vreede
Presenter:
Yiyu Shen, Delft Univ. of Technology, The Netherlands
MO3B-4 : A 2x2 802.11ac WiFi Transceiver Supporting Per Channel 160MHz Operation in 28nm CMOS
Authors:
Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, Wen-Ming Chang, Chang-Ming Lai, Tao Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, Wei-Hsiu Hsu, Jing-Hong Zhan
Presenter:
Jing-Hong Zhan, MediaTek, Inc., Taiwan
MO3B-5 : A Current-Efficient Wideband Cellular RF Receiver for Multi-Band Inter- and Intra-Band Carrier Aggregation Using 14nm FinFET CMOS
Authors:
Youngmin Kim, Pilsung Jang, Taehwan Jin, Jaeseung Lee, Heeseon Shin, Suseob Ahn, Jungyeol Bae, Junghwan Han, Seungchan Heo, Thomas Byunghak Cho
Presenter:
Youngmin Kim, Samsung Electronics Co., Ltd., Korea, Republic of
MO3D:
X Band PAs and Beyond
Chair: 
Jeffrey Walling
Chair organization: 
Univ. of Utah
Co-chair: 
Ranjit Gharpurey
Co-chair organization: 
Univ. of Texas at Austin
Location: 
313B
Abstract: 
This session describes an array of techniques to address the challenges of operating PAs at high frequencies and wide bandwidths. These capabilities will serve as enablers for emerging 5G communications systems.
Presentations in this session
MO3D-1 : Fully Integrated CMOS X-Band Power Amplifier Quad With Current Reuse and Dynamic Digital Feedback (DDF) Capabilities
Authors:
Florian Bohn, Behrooz Abiri, Ali Hajimiri
Presenter:
Florian Bohn, California Institute of Technology, United States
MO3D-2 : A 42-46.4% PAE Continuous Class-F Power Amplifier With Cgd Neutralization at 26-34 GHz in 65 nm CMOS for 5G Applications
Authors:
Sheikh Nijam Ali, Pawan Agarwal, Shahriar Mirabbasi, Deukhyoun Heo
Presenter:
Sheikh Nijam Ali, Washington State Univ., United States
MO3D-3 : Waveform Engineering in a mm-Wave Stacked-HBT Switching Power Amplifier
Authors:
Kunal Datta, Hossein Hashemi
Presenter:
Kunal Datta, Univ. of Southern California, United States
MO3D-4 : Linear CMOS Power Amplifier at Ka-Band With Ultra-Wide Video Bandwidth
Authors:
Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, Juho Son, Bumman Kim
Presenter:
Daechul Jeong, Pohang Univ. of Science and Technology, Korea, Republic of
MO3D-5 : Adaptive Gain and Phase Adjustment for Local Linearization of Power Amplifiers of Micro/MM-Wave Phase Arrays
Authors:
Farid Shirinfar, Reza Rofougaran, Sudhakar Pamarti
Presenter:
Farid Shirinfar, Univ. of California, Los Angeles, United States
15:30 - 17:10
MO4A:
Low-Power Transceivers
Chair: 
Gernot Hueber
Chair organization: 
NXP Semiconductors
Co-chair: 
Yao-Hong Liu
Co-chair organization: 
IMEC
Location: 
312
Abstract: 
Wireless transceivers are one of the most power-consuming building blocks in IoT sensor nodes. In this session, several low-power transceiver design techniques will be presented, including crystal-less and stacked-RF designs. In addition, three fully-integrated RF transceivers for emerging IoT standards, IEEE802.11ah and NFC-ISO/IEC1443, will be shown.
Presentations in this session
MO4A-1 : Crystal-Free Narrow-Band Radios for Low-Cost IoT
Authors:
Brad Wheeler, Filip Maksimovic, Nima Baniasadi, Sahar Mesri, Osama Khan, David Burnett, Ali Niknejad, Kris Pister
Presenter:
Brad Wheeler, Univ. of California, Berkeley, United States
MO4A-2 : A 4mW-RX 7mW-TX IEEE 802.11ah Fully-Integrated RF Transceiver
Authors:
Ao Ba, Kia Salimi, Paul Mateman, Pepijn Boer, Johan van den Heuvel, Jordy Gloudemans, Johan Dijkhuis, Ming Ding, Yao-Hong Liu, Christian Bachmann, Guido Dolmans, Kathleen Philips
Presenter:
Ao Ba, Holst Centre, The Netherlands
MO4A-3 : A Sub-1V, 2.8dB NF, 475µW Coupled LNA for Internet of Things Employing Dual-Path Noise & Nonlinearity Cancellation
Authors:
Mustafijur Rahman, Ramesh Harjani
Presenter:
Mustafijur Rahman, Univ. of Minnesota, Twin Cities, United States
MO4A-4 : A Fully Integrated Reconfigurable Low-Power Sub-GHz Transceiver for 802.11ah in 65nm CMOS
Authors:
Meng Wei, Zheng Song, Peiyi Li, Jianfu Lin, Junfeng Zhang, Jiachen Hao, Baoyong Chi
Presenter:
Meng Wei, Tsinghua Univ., China
MO4A-5 : A 3.4Mbps NFC Card Emulator Supporting 40mm2 Loop Antenna
Authors:
Tieng Ying Choke, Ying Chow Tan, Chin Heng Leow, Junmin Cao, Liming Jin, Huajiang Zhang, Hon Cheong Hor, Eng Chuan Low, Weimin Shu, Osama Shana'a
Presenter:
Tieng Ying Choke, MediaTek, Singapore Pte. Ltd., Singapore
MO4B:
RF Circuits for Emrging Applications and Gigabit Optical Links
Chair: 
Fred Lee
Chair organization: 
Google, Inc.
Co-chair: 
Ayman Fayed
Co-chair organization: 
Ohio State Univ.
Location: 
313A
Abstract: 
The first three presentations cover new applications of RF circuit design. First, an RFDAC is designed in a FINFET process and tackles challenging mismatch issues. Next, a galvanic isolator using lateral RF coupling techniques achieves 3.3kVrms isolation. Finally, an implantable RF bio-sensing interface chip is designed using optical and RF backscatter techniques. The final two papers focus on drivers for gigabit optical links. A SiGe linear modulator driver is presented which achieves 4.8-Vpp differential swing for rates up to 120 GBaud. The final paper presents a 15 Gbaud PAM4 laser driver with active termination in 65-nm CMOS.
Presentations in this session
MO4B-1 : A 12-b, 1-GS/s 6.1 mW Current-Steering DAC in 14 nm FinFET With 80 dB SFDR for 2G/3G/4G Cellular Application
Authors:
Jaekwon Kim, Woojin Jang, Yanghun Lee, Seunghyun Oh, Jongwoo Lee, Thomas Byunghak Cho
Presenter:
Jaekwon Kim, Samsung Electronics Co., Ltd., Korea, Republic of
MO4B-2 : CMOS Integrated Galvanically Isolated RF Chip-to-Chip Communication Utilizing Lateral Resonant Coupling
Authors:
Mahdi Javid, Richard Burton, Karel Ptacek, Jennifer Kitchen
Presenter:
Mahdi Javid, Arizona State Univ., United States
MO4B-3 : A 200µm x 200µm x 100µm, 63nW, 2.4GHz Injectable Fully-Monolithic Wireless Bio-Sensing System
Authors:
Stephen O'Driscoll, Sean Korhummel, Peng Cong, Kannan Sankaragomathi, You Zou, Jiang Zhu, Travis Deyle, Alireza Dastgheib, Bo Lu, Michael Tierney, Jingru Shao, Christian Gutierrez, Stephen Jones, Haunfen Yao
Presenter:
Stephen O'Driscoll, Verily (Google) Life Sciences, United States
MO4B-4 : SiGe BiCMOS Linear Modulator Drivers With 4.8-Vpp Differential Output Swing for 120-GBaud Applications
Authors:
Robert Baker, James Hoffman, Peter Schvan, Sorin Voinigescu
Presenter:
Robert Baker, Univ. of Toronto, Canada
MO4B-5 : A 32Gb/s-NRZ, 15GBaud/s-PAM4 DFB Laser Driver With Active Back-Termination in 65nm CMOS
Authors:
Bozhi Yin, Nan Qi, Jingbo Shi, Xi Xiao, Daigao Chen, Miaofeng Li, Zhiyong Li, Jiangbing Du, Zuyuan He, Rui Bai, Yi Wang, Jun Zheng, Fred Chang, Huanlin Zhang, Patrick Chiang
Presenter:
Bozhi Yin, Fudan Univ., China
MO4D:
Reconfigurable Receiver Front-Ends
Chair: 
Eric Klumperink
Chair organization: 
Univ. of Twente
Co-chair: 
Ramesh Harjani
Co-chair organization: 
Univ. of Minnesota
Location: 
313B
Abstract: 
Various novel analog and digital techniques that are employed in the realization of reconfigurable RF front-ends will be presented. These allow for high blocker and self-interference resiliency, full-duplex operation, and efficient use of power and silicon area. Examples include use of non-reciprocal elements, mixer-first receiver innovations, code domain operation and compressive sensing.
Presentations in this session
MO4D-1 : A Direct RF-to-Information Converter for Reception and Wideband Interferer Detection Employing Pseudo-Random LO Modulation
Authors:
Tanbir Haque, Mathew Bajor, Yudong Zhang, Jianxun Zhu, Zarion Jacobs, Robert Kettlewell, John Wright, Peter Kinget
Presenter:
Tanbir Haque, Columbia Univ., United States
MO4D-2 : A 0.3 GHz to 1.4 GHz N-Path Mixer-Based Code-Domain RX With TX Self-Interference Rejection
Authors:
Abhishek Agrawal, Arun Natarajan
Presenter:
Abhishek Agrawal, Oregon State Univ., United States
MO4D-3 : A 0.7 to 1 GHz Switched-LC N-Path LNA Resilient to FDD-LTE Self-Interference at ≥40 MHz Offset
Authors:
Gengzhen Qi, Barend van Liempd, Pui-In Mak, Rui P. Martins, Jan Craninckx
Presenter:
Gengzhen Qi, University Of Macau, China
MO4D-4 : A Mixer-First Receiver with Enhanced Selectivity by Capacitive Positive Feedback Achieving +39dBm IIP3 and
Authors:
Yuanching Lien, Eric Klumperink, Bernard Tenbroek, Jon Strange, Bram Nauta
Presenter:
Yuanching Lien, Univ. of Twente, The Netherlands
MO4D-5 : 85-110 GHz CMOS Tunable Nonreciprocal Transmission Line With 45 dB Isolation for Wideband Transceivers
Authors:
Chang Yang, Ping Gui
Presenter:
Chang Yang, Southern Methodist Univ., United States
Tue. 6 June
8:00 - 9:40
TU1A:
RF Front-End Building Blocks
Chair: 
Gary Zhang
Chair organization: 
Guangdong Univ. of Technology
Co-chair: 
Bodhisatwa Sadhu
Co-chair organization: 
IBM T.J. Watson Research Center
Location: 
312
Abstract: 
In this session, various RF front-end building blocks such as mixers, filters and phase shifters are discussed. Furthermore, advanced techniques such as harmonic rejection and feed-forward linearization are presented. These components and techniques are applicable to phased arrays, MIMO systems and highly linear receivers.
Presentations in this session
TU1A-1 : A Bi-Directional, X-Band 6-Bit Phase Shifter for Phased Array Antennas Using an Active DPDT Switch
Authors:
Yunyi Gong, Moon-Kyu Cho, John Cressler
Presenter:
Yunyi Gong, Georgia Institute of Technology, United States
TU1A-2 : Low Power Highly Linear Band-Pass/Band-Stop Filter for 2-4 GHz With Less than 1% of Fractional Bandwidth in 0.13 um CMOS Technology
Authors:
Laya Mohammadi, Kwang-Jin Koh
Presenter:
Laya Mohammadi, Virginia Polytechnic Institute and State Universit, United States
TU1A-3 : A Feedforward Linearization Technique Implemented in IF Band for Active Down-Conversion Mixers
Authors:
Hao Li, Xiao Yang, Carlos Saavedra
Presenter:
Hao Li, Queen's Univ., Canada
TU1A-4 : A 1-30 GHz 3-Bit Vector Modulator Based on Ultra-Wideband IQ-Generation for MIMO-Radar-Systems in SiGe BiCMOS
Authors:
Benedikt Welp, Askold Meusling, Klaus Aufinger, Nils Pohl
Presenter:
Benedikt Welp, Fraunhofer FHR, Germany
TU1A-5 : A 0.05-6 GHz Voltage-Mode Harmonic Rejection Mixer With up to 30 dBm In-Band IIP3 and 35 dBc HRR in 32 nm SOI CMOS
Authors:
Kerim Kibaroglu, Gabriel Rebeiz
Presenter:
Kerim Kibaroglu, Univ. of California at San Diego, United States
TU1B:
Advanced Mm-Wave Circuit Techniques
Chair: 
Hua Wang
Chair organization: 
Georgia Institute of Technology
Co-chair: 
Pierre Busson
Co-chair organization: 
STMicroelectronics
Location: 
313A
Abstract: 
This session presents advanced circuit techniques for basic building blocks in mm-wave and above systems. The first paper demonstrates a W-band CMOS amplifier with broadband neutralization technique operating at 0.5V supply. The second paper shows a 77GHz mm-Wave active reflector for vehicular radar and other applications. The third paper proposes an advanced broadband ESD protection design for mm-Wave front-end circuits. The fourth paper presents an in-antenna active power combining at 240GHz. The session is concluded with a mm-Wave transformer-based injection locking frequency divider (ILFD) in CMOS with 62.9% tuning range.
Presentations in this session
TU1B-1 : An 80-106 GHz CMOS Amplifier With 0.5 V Supply Voltage
Authors:
Kosuke Katayama, Shuhei Amakawa, Kyoya Takano, Takeshi Yoshida, Minoru Fujishima, Kazuya Hisamitsu, Hirotaka Takatsuka
Presenter:
Kosuke Katayama, Hiroshima University, Japan
TU1B-2 : A 77-GHz Active Millimeter-Wave Reflector for FMCW Radar
Authors:
Sadegh Dadash, Juergen Hasch, Sorin Voinigescu
Presenter:
Sadegh Dadash, Univ. of Toronto, Canada
TU1B-3 : A High-Performance Slow-Wave CPW With ESD Protection for Ultraflat Band Millimeter-Wave Applications
Authors:
Wei Gao, Handoko Linewih, Suh-Fei Lim, Jian-Hsing Lee, Sern-Ee Leang
Presenter:
Wei Gao, GLOBALFOUNDRIES, Singapore
TU1B-4 : Circuit Building Blocks for Efficient In-Antenna Power Combining at 240 GHz With non-50 Ohm Amplifier Matching Impedance
Authors:
Christian von Vangerow, Benjamin Goettel, Herman Ng, Dietmar Kissinger, Thomas Zwick
Presenter:
Christian von Vangerow, Karlsruhe Institute of Technology, Germany
TU1B-5 : A 27.9-53.5-GHz Transformer-Based Injection-Locked Frequency Divider With 62.9% Locking Range
Authors:
Jingzhi Zhang, Huihua Liu, Yunqiu Wu, Chenxi Zhao, Kai Kang
Presenter:
Jingzhi Zhang, Univ. of Electronic Science and Technology of China, China
TU1D:
Reconfigurable Multi-Mode PAs
Chair: 
Patrick Reynaert
Chair organization: 
Katholieke Univ. Leuven
Co-chair: 
Gary Hau
Co-chair organization: 
Qualcomm Technologies, Inc.
Location: 
313B
Abstract: 
This session describes various techniques to improve PA performances over wide bandwidth and output power ranges. These architectures address the trade-off needed in current and next generation front-end.
Presentations in this session
TU1D-1 : A Digital mm-Wave PA Architecture With Simultaneous Frequency and Back-off Reconfigurability
Authors:
Chandrakanth Chappidi, Xue Wu, Kaushik Sengupta
Presenter:
Chandrakanth Chappidi, Princeton Univ., United States
TU1D-2 : A Digitally-Tuned Triple-Band Transformer Power Combiner for CMOS Power Amplifiers
Authors:
Rahul Singh, Jeyanandh Paramesh
Presenter:
Rahul Singh, Carnegie Mellon Univ., United States
TU1D-3 : A Split-Array, C-2C Switched-Capacitor Power Amplifier in 65nm CMOS
Authors:
Zhidong Bai, Wen Yuan, Ali Azam, Jeffrey Walling
Presenter:
Zhidong Bai, Univ. of Utah, United States
TU1D-4 : A 20dBm Outphasing Class E PA With High Efficiency at Power Back-off in 65nm CMOS Technology
Authors:
Ali Ghahremani, Anne-Johan Annema, Bram Nauta
Presenter:
Ali Ghahremani, Univ. of Twente, The Netherlands
TU1D-5 : An S/X-Band CMOS Power Amplifier Using a Transformer-Based Reconfigurable Output Matching Network
Authors:
Jaeyong Ko, Sungho Lee, Sangwook Nam
Presenter:
Jaeyong Ko, Seoul National Univ., Korea, Republic of
10:00 - 11:40
TU2A:
Full-Duplex, Interference-Resilient and Harmonic-Rejection Receivers
Chair: 
Renaldi Winoto
Chair organization: 
Marvell Semiconductor, Inc.
Co-chair: 
Raja Pullela
Co-chair organization: 
MaxLinear, Inc.
Location: 
312
Abstract: 
Modern communication systems require a wide dynamic range to co-exist with interferers, both self generated and from other sources in the environment. In this session, system and circuit techniques for interference cancellation, harmonic rejection and narrow-band notching are presented. The techniques presented here improve immunity to blockers and thus enable next generation systems, such as full-duplex receivers.
Presentations in this session
TU2A-1 : Low Power Wideband Receiver With RF Self-Interference Cancellation for Full-Duplex and FDD Wireless Diversity
Authors:
Ehsan Kargaran, Saheed Tijani, Giacomo Pini, Danilo Manstretta, Rinaldo Castello
Presenter:
Saheed Tijani, Univ. of Pavia, Italy
TU2A-2 : An FD/FDD Transceiver With RX Band Thermal, Quantization,and Phase Noise Rejection and >64dB TX Signal Cancellation
Authors:
Sameet Ramakrishnan, Lucas Calderin, Ali Niknejad, Borivoje Nikolic
Presenter:
Lucas Calderin, Univ. of California, Berkeley, United States
TU2A-3 : A CMOS UWB Receiver With Reconfigurable Notch Filters for Narrow-Band Interferers
Authors:
Paria Sepidband, Kamran Entesari
Presenter:
Paria Sepidband, Texas A&M Univ., United States
TU2A-4 : A Full-Duplex Receiver With 80MHz Bandwidth Self-Interference Cancellation Circuit Using Baseband Hilbert Transform Equalization
Authors:
Ahmed El Sayed, Abdelrahman Ahmed, Amit Mishra, Amir Masnadi, Sang-Pil Woo, Yang-Seok Choi, Shahriar Mirabbasi, Sudip Shekhar
Presenter:
Ahmed El Sayed, Univ. of British Columbia, Canada
TU2A-5 : A Wideband Receiver Employing PWM-Based Harmonic Rejection Downconversion
Authors:
Heechai Kang, Wei-Gi Ho, Vineet Singh, Ranjit Gharpurey
Presenter:
Heechai Kang, Univ. of Texas at Austin, United States
TU2B:
System-on-Chip for Millimeter-Wave and Above
Chair: 
Vito Giannini
Chair organization: 
UHNDER Inc
Co-chair: 
Tim LaRocca
Co-chair organization: 
Northrop Grumman Aerospace Systems
Location: 
313A
Abstract: 
This session will focus on highly-integrated System-on-Chip solutions for sensing and communication applications at millimeter-wave and sub-millimeter-wave frequencies. The papers demonstrate state-of-the-art performance using integrated on-chip antennas, multi-channel beamforming networks, and/or advanced transceiver architectures. These solutions may enable next-generation MIMO radar, ultra-high resolution imaging and wireless point-to-point bandwidth efficient QAM backhaul radio.
Presentations in this session
TU2B-1 : Highly-Miniaturized 2-Channel mm-Wave Radar Sensor With On-Chip Folded Dipole Antennas
Authors:
Herman Ng, Wael Ahmad, Maciej Kucharski, Jeng-Hau Lu, Dietmar Kissinger
Presenter:
Herman Ng, IHP Microelectronics, Germany
TU2B-2 : Fully-Scalable 2D THz Radiating Array: A 42-Element Source in 130-nm SiGe With 80-μW Total Radiated Power at 1.01 THz
Authors:
Zhi Hu, Ruonan Han
Presenter:
Zhi Hu, Massachusetts Institute of Technology, United States
TU2B-3 : A Wideband SiGe BiCMOS Transceiver Chip-set for High-Performance Microwave Links in the 5.6-43.5 GHz Range
Authors:
Yves Baeyens, Shahriar Shahramian, Bahar Jalali_Farahani, Pascal Roux, Joe Weiner, Amit Singh, Maurizio Moretto, Pascal Boutet, Pierre Lopez
Presenter:
Yves Baeyens, Nokia / Bell-Labs, United States
TU2B-4 : A Fully-Integrated 94-GHz 32-Element Phased-Array Receiver in SiGe BiCMOS
Authors:
Jean-Olivier Plouchart, Wooram Lee, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Emre Apaydin, Alberto Valdes-Garcia
Presenter:
Jean-Olivier Plouchart, IBM T.J. Watson Research Center, United States
TU2B-5 : A 71-86 GHz Bidirectional Image Selection Transceiver Architecture
Authors:
Najme Ebrahimi, James Buckwalter
Presenter:
Najme Ebrahimi, Univ. of California at San Diego, United States
TU2D:
Power Amplifiers in Advanced Technologies
Chair: 
Margaret Szymanowski
Chair organization: 
NXP Semiconductors
Co-chair: 
Nick Cheng
Co-chair organization: 
Skyworks Solutions
Location: 
313B
Abstract: 
This session presents PA designs in cutting edge technologies, including GaN, GaAs, SiGe, SOI and FinFET CMOS, to address 5G and mm-wave systems.
Presentations in this session
TU2D-1 : Peaking PA Bias Circuit for an APT CMOS Doherty PA
Authors:
Joonhoi Hur, Paul Draxler, Joung Won Park, Anthony Segoria, Vladimir Aparin
Presenter:
Joonhoi Hur, Qualcomm Technologies, Inc., United States
TU2D-2 : An X-Band Inverse Class-F SiGe HBT Cascode Power Amplifier With Harmonic-Tuned Output Transformer
Authors:
Inchan Ju, John Cressler
Presenter:
Inchan Ju, Georgia Institute of Technology, United States
TU2D-3 : A 6−18 GHz GaN Distributed Power Amplifier Using Reactive Matching Technique and Simplified Bias Network
Authors:
Hongjong Park, Sangho Lee, Kwangseok Choi, Jihoon Kim, Hyosung Nam, Jaeduk Kim, Wangyong Lee, Changhoon Lee, Junghyun Kim, Youngwoo Kwon
Presenter:
Hongjong Park, Seoul National Univ., Korea, Republic of
TU2D-4 : A Ka-Band Asymmetrical Stacked-FET MMIC Doherty Power Amplifier
Authors:
Duy Nguyen, Thanh Pham, Anh-Vu Pham
Presenter:
Duy Nguyen, Univ. of California, Davis, United States
TU2D-5 : A 73GHz PA for 5G Phased Arrays in 14nm FinFET CMOS
Authors:
Steven Callender, Stefano Pellerano, Christopher Hull
Presenter:
Steven Callender, Intel Corp., United States
11:45 - 12:45
2:
Who Wants to be a Millimeterwavionaire?
Organizer: 
Earl McCune, Sherry Hess, Bodhisatwa Sadhu, Oren Eliezer
Organizer organization: 
Eridan Communicatinos, AWR Corp., IBM Research, PHAZR
Abstract: 
Two teams of contestants, including preselected and randomly selected contestants from the audience, will compete in answering questions on RF and microwave theory and history, including IMS/RFIC conference trivia.  Prizes will be awarded to the contestants, as well as to others in the audience who may be called upon for answers.  Bring your lunch and be prepared for a great deal of entertainment and a little bit of learning too!

Contestants:    
You’ll find out when you get there!   Maybe you will be one of them?