Phased-Array-Compatible Area-Efficient D-Band Power Amplifiers in 45 RF SOI based on Cascade Stacking

This work presents a high-power, area-efficient PA at 140GHz in 45 RF SOI CMOS. A cascade-stacked architecture that can sustain a larger output voltage swing is utilized to achieve a higher saturated output power (PSAT) in an area-efficient manner while allowing the PA to operate at the same standard supply domain. This architecture also allows the DC current of the stacked stages to be decoupled, enabling independent bias optimization for peak power-added efficiency (PAE). A two-way power-combined PA using this architecture is also implemented to boost the PSAT further. Measured results indicate that the unit PA operating at 1/1.2V achieves a gain of 30.8/32.7dB, PSAT of 15.1/16.4dBm, and PAE of 13.4/12.7%, while the two-way power-combined PA achieves a gain of 30.8/32.1dB, PSAT of 17.9/19.2dBm, and peak PAE of 12.7/12.2%. The achieved PSAT and ITRS FoM represent the highest among state-of-the-art 140GHz CMOS PAs.