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A D-Band Power Amplifier with Optimized Common-Mode Behaviour Achieving 32Gb/s in 22-nm FD-SOI
This paper presents a high linearity and high backoff efficiency power amplifier for D-band communication in 22 nm CMOS FD-SOI technology. Fully differential eight-way power combining with extremely low insertion loss is implemented, enhancing the common-mode-rejection-ratio, output power and linearity with bypass capacitors placement and sizing. Cascading moderate and deep class AB stages, together with a careful choice of the value of common mode stability resistors, further improves amplifier's linearity. The small-signal gain and bandwidth (BW) are 16 dB and 21GHz. The OP1dB and Psat are 11.4 dBm, 14.6 dBm while maximum PAE and 6dB backoff PAE are 10.6 % and 2.8 % respectively. To the authors' best knowledge, this PA achieves the highest average output power and efficiency during modulated signals measurement among CMOS in literature D-band PAs. A data-rate of 32 Gb/s using 16-QAM is demonstrated at 8.1 dBm average output power and 4.2 % average PAE.