A D-Band Power Amplifier with Optimized Common-Mode Behaviour Achieving 32Gb/s in 22-nm FD-SOI

This paper presents a high linearity and high backoff efficiency power amplifier (PA) for D-band (110–170 GHz) communication in 22 nm CMOS FD-SOI technology. Fully differential eight-way power combining with extremely low insertion loss is implemented, enhancing the common-mode-rejection-ratio (CMRR), output power and linearity with bypass capacitors placement and sizing. Cascading moderate and deep class AB stages, together with a careful choice of the value of common mode stability resistors, further improves amplifier’s linearity. The small-signal gain and bandwidth (BW) are 16 dB and 21GHz. The OP1dB and Psat are 11.4 dBm, 14.6 dBm while maximum PAE and 6dB backoff PAE are 10.6% and 2.8% respectively. The highest demonstrated data-rate is 32 Gb/s, using 16-QAM modulation scheme at an average output power and PAE of 8.1 dBm and 4.2% respectively.