A Double Balanced Frequency Doubler Achieving 70% Drain Efficiency and 25% Total Efficiency

This work presents a compact double-balanced frequency doubler achieving better than 70% drain and 25% total power efficiency. Complementary NMOS and PMOS devices enable a truly double-balanced frequency doubler. This work’s complementary current reuse structure implements voltage scaling in the device. Voltage scaling enables each device to operate at half the effective supply voltage improving efficiency. The stacked design with inverted NMOS and PMOS positions allows deep class C biasing for an effective VGS of negative 0.5V without on-chip negative voltage generation. These techniques enable a high-efficiency frequency doubler, showing nearly 3× higher drain efficiency and 25% higher total efficiency than previously published frequency doublers. This device offers almost 60% higher efficiency than devices without active second harmonic gain. This work also shows wide-band operation with over 23GHz RF BW and excellent output power of 9.8dBm. Implemented in a commercial 45nm SOI technology, this device presents one of the smallest area consumptions in the literature thanks to the complementary current reuse implementation.