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#### A 10:1 Bandwidth 2.5–25GHz Multi-Standard High-Linearity 6-Bit Phased-Array Receiver Front-End with Quad-Pole I/Q Network and 2.7° RMS Phase Error

In this paper, a 2.5–25 GHz high-linearity phased-array receiver front-end is proposed and demonstrated. The design is based on a novel phase-shifter (PS) and is implemented using a 4-pole voltage-to-current (V-I) mode quadrature all-pass filter (QAF) and a high linearity common-base (CB) vector modulator (VM). An RMS phase error of 2.7–3.2° over a 10:1 frequency range is achieved without any calibration. An IP1dB of -21 to -28 dBm is measured at a power consumption of 96 mW. The chip is implemented in the Tower Semi 90nm SBC18S5 SiGe BiCMOS process.