A 0.2–25GHz Inductorless Complementary Pseudo-Push-Push Frequency Doubler

An inductorless and buffer-less complementary pseudo-push-push frequency doubler (CP3FD) demonstrating expansive operational bandwidth and low DC power consumption. The pseudo-push-push operation is implemented by a synergistic common-gate and common-source configuration, establishing a single-ended resistive impedance at the input and thereby allowing substantial expansion of the bandwidth. Additionally, a complementary structure is proposed, which not only reduces power consumption by current reuse but also improves the fundamental rejection ratio (FRR) significantly. Fabricated in a 65-nm CMOS process, the proposed CP3FD measures a maximum conversion gain (CG) of -10.1 dB and a 3-dB frequency range from 0.2 to 25 GHz, with an input signal power of 0 dBm. The core area of the chip is only 39 × 65 µm².