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Device Fixtures, Calibration Approaches and Test Benches for Large Signal DUT Model Validation at Sub-THz
The performance increase of state-of-the-art silicon based technologies and the interest in commercial applications targeting operation above 100GHz operation (ie 6G and high resolution automotive radars) is placing more stringent requirements on small and large signal model validation at such frequencies. Compact models are often extracted via a set of low-frequency and RF measurements up to 67GHz, employing de-embedding techniques making use of test fixture dummies which are not suited for model validation in the >100GHz range. Moreover, classical test-benches used for large signal measurements (ie scalar and power meter based) do not provide the sensitivity and accuracy required for the validation of compact model of small transistor cells. In this contribution we will review test fixture approaches to transfer the accuracy provided by accurate calibration techniques (ie TRL and multi-line TRL) to the intrinsic transistor plane. Then the challenges and the solutions to enable vector corrected power levelled s-parameters and large signal test benches will be introduced, presenting small and large signal model validation of state-of-the-art CMOS devices in the above-100GHz range.