Analog IC design centering and modeling challenges at mm-waves: a III-V perspective with a peak at RF CMOS

Recent focus in mm-Wave technology for 5G communications demand transceiver power added efficiency-aware MMIC and system co-design. While mm-Wave device and circuit performance in both research and commercial literature reflect tremendous progress, there still is a considerable effort towards developing scalable models that can reliably capture advanced devices under high-frequency and large-signal operation. Especially above 100 GHz, transistor models are typically not as well validated as their lower frequency counterparts, making mm-Wave IC design challenging, often requiring 1-2 design cycles to arrive at the intended performance. Much of the difficulty stems from the lack of comprehensive statistical models and limited understanding of how device and wiring environment variability affects various circuit topologies at higher frequencies. This talk will start by reviewing leading mm-Wave technologies and modeling paradigms. The second part will benchmark mm-Wave devices and topologies for LNA, mixer and PAs diving into the bandwidth, gain and efficiency trade-off. In the third part, we will analyze the robustness of various mm-Wave gain stage and power cells topologies under realistic device process limits dividing the study in 30-75GHz, 75-110GHz and 110-170GHz frequency bands. The effect of passive component fabrication tolerance on matching and combining elements will also be analyzed across the same frequencies. Finally, we will discuss suitable feedback and compensation methods that are frequency-band specific.