A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology

This article presents a wideband 12bit 6GS/s TI SAR ADC implemented in a 28nm CMOS technology addressing FMCW based radar, as well as instrumentation applications demanding excellent ADC linearity. The proposed ADC makes use of a wideband front-end featuring two ranks of pseudo-differential push-pull buffers to distribute the input signal to 19 12bit 375MS/s SAR-ADC lanes. Each lane takes advantage of a sub-2 radix split CDAC, an isolating distributed sample T-switch and a loop-unrolled comparator. The ADC system features an on-chip digital calibration to correct inter-channel mismatch effects such as gain, offset and sample-phase mismatch. Measurement results reveal an SNDR and SFDR of 50 dB and 62.8 dBc respectively for a 1Vppd single tone sine wave input signal across the entire Nyquist-band with an HD3 of 72.7 dBc at Nyquist. The complete ADC system draws 2.5W, resulting in a Schreier Figure-of-Merit of 145/141 dB for low and high-frequency inputs respectively.