A 40GS/s 8bit Time-Interleaved Time-Domain ADC Featuring SFDR-Enhanced Sample-and-Hold Circuit and Power-Efficient Adaptive Pulse Generator in 28nm CMOS

This paper presents a 40GS/s, 8-bit time-interleaved time-domain GRO-ADC fabricated in 28nm CMOS. An adaptive-working pulse generator eliminates the unnecessary pulse of previous topology and minimize the pulse generation power. The sampling front-end employs a linearity-enhanced boosted switch that supports short-time and high input voltage sampling, as well as a switched class-AB output buffer for low-power driving and nonlinear coupling suppression at high input frequency. Also, the multi-channel interleaved architecture frees the GRO-ADC from single channel calibration and reduce the sub-ADC design complexity. The TI GRO-ADC prototype is fabricated in a 28 nm CMOS process with an active area of 0.015 mm2. It scores a measured peak SNDR of 40.3 dB and SFDR of 56 dB, respectively, at the conversion rate of 40 GS/s, along with the Walden figures of merit (FoMw) of 41.6 fJ/conversion step.