Chiplet Interconnect Solutions

The exponential growth of AI systems has driven their compute performance requirement close to 10x/year. Not only has Moore’s law slowed down significantly, limiting the scaling of processor chips, but more importantly the processor-to-processor and processor-to-memory bandwidths are in fact leading to much more serious performance limitations. The chiplet system-in-package (SiP) enables connecting processors in form of chiplets with die-to-die PHYs at an order of magnitude higher speeds than existing approaches. Additionally, in-package memory chiplets and/or memory PHY chiplets can be leveraged to substantially increase the processor-memory bandwidth using die-to-die PHYs. To practically connect chiplets, die-to-die PHY standards are necessary. Industry has already proposed BoW or UCIe for general die-to-die connectivity. This talk presents Universal Memory Interconnect (UMI) which is a chiplet interconnect technology optimized for die-to-memory PHY and all its key features and benefits.