Design Technology Co-Optimization for RF/mmWave Circuits with Circuit Under Inductor (CUI) in FinFET CMOS Technologies

This paper presents an approach, circuit under inductor (CUI), to reduce chip area as a solution for design technology co-optimization (DTCO) in sub-10-GHz RF and millimeter-wave (mmWave) applications. With the use of CUI and dual ultra-thick metal (DUTM) scheme as well as design guidelines, a smaller footprint can be obtained for a 2.4-GHz LC-VCO in 6-nm CMOS and a 28-GHz PA in 16-nm CMOS while the RF performance is less impacted compared to the reference case. For the 2.4-GHz LC-VCO with the CUI, the measured phase noise at a 1-MHz offset and tuning range are -117.3 dBc/Hz and 21%, respectively. As for the 28-GHz PA with the CUI, the Psat of 19.7 dBm and the peak PAE of 38.1% are achieved. The measured results successfully manifest the feasibility of the proposed CUI.