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A Path to 200+Gb/s Transceiver Design for Electrical Interconnects
Demand for higher bandwidth of inter-chip data communication through electrical interconnects is stronger than ever before due to explosive growth of global data generation, processing, and communication. Plausible but energy efficient solutions to keep increasing per-pin data-rate of electrical wireline transceivers at a cadence of 2x per 3–4 years have been actively investigated in academia and industries. Transceiver solutions for 100Gb/s have been successfully laid out, implemented, and demonstrated by many players in the past couple of years and now 200Gb/s solutions are being explored. In this presentation, we will review circuit design techniques that were used to implement 100–200Gb/s transceivers and discuss challenges/options to extend the per-pin data-rate further.