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Generating “Efficient” D-Band Power Using Nanoscale CMOS Technology
CMOS output power is limited due to low breakdown voltage, and CMOS power gain is limited above 100GHz due to limited fmax, making efficient power generation especially difficult. Fortunately, arrays of transmitters reduce EIRP requirements by array size squared, reducing power requirements from 100mW–1W for typical indoor/outdoor requirements to more modest power levels of ~10mW–100mW. As we will highlight in this presentation, generation of these power levels is very challenging, requiring innovation in power combining and transistor matching.