A Compact Ultra-High-Linearity 7-to-20GHz Passive Mixer Achieving up to 37dBm IIP3 and 25.1dBm IP1dB in 45nm CMOS SOI

This paper presents an ultra-high-linearity 7–20 GHz passive mixer demonstrating state-of-the-art linearity performance at a relatively low power consumption. The design adopts multiple techniques like low-impedance operation, series-stacked transistors, and semi-floating switch gates to boost the mixer linearity. Power-efficient stacked LO drivers are used to drive the mixer resulting in improved mixer IIP3 efficiency. The mixer prototype is fabricated in GlobalFoundaries 45nm CMOS SOI technology and has a measured conversion loss of 8–11.7 dB with a 3-dB RF bandwidth of 7–20 GHz. The mixer achieves an input P1dB of 20.3–25.1 dBm and has a measured IIP3 of 25.3–37 dBm at 7–20 GHz while consuming 0.07–0.43 W. To the best of the authors’ knowledge, this is the highest linearity performance for a mixer implemented in a scaled CMOS technology. Application areas are wideband receivers for base stations and wideband phased-arrays.