A 0.2-to-39.2GHz 66.2-fs Jitter and –71.3dBc Spur Sub-Sampling PLL Using DAC-Based Constant Control Voltage Compensator and Quad-Mode 2nd Harmonic Filtering Oscillator

In this paper, an ultra-wideband fast-locking PLL with low jitter and spur is proposed. A digital-to-analog based constant control voltage compensator is introduced to achieve constant control voltage of oscillator in PLL. Here, the less control voltage variation obtains fast-locking and low jitter and spur variations. Besides, the mm-wave quad-mode 2nd harmonic filtering oscillator is integrated in the PLL to achieve the low out-of-band phase noise within a wide frequency range. The tail resonator is injected in four times of common-mode current, which enhances the 2nd harmonic shaping. Meanwhile, the two-circles transformer with in-phase coupling is implemented for improving the quality factor of oscillation resonator. Measurements exhibit an output frequency range of 198% from 0.2 to 39.2GHz. The PLL achieves 66.2fsrms jitter, –71.3dBc spur, and less than 200ns locking time.