Low-Jitter PLLs for Advanced Wireless Transceivers

PLLs and frequency synthesizers are key building blocks in wireless transceivers. With the trend of higher data-rate, higher carrier frequency and higher order of modulation in the advanced wireless applications, local oscillators (LOs) of sub-100fsrms jitter are required given a limited power budget. This talk presents the recent trends and design techniques on low-jitter fractional-N PLLs from both the block and system level. Both analog and digital calibration techniques will be discussed in detail to strive for low jitter and high figure-of-merit. Finally, a low-jitter LO generation design example for 5G mm-wave cellular transceivers will be demonstrated.