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Next-Generation Electrical Interconnects: Chips and Chiplets
Data-center and compute applications continue to demand higher bandwidth in electrical interconnects, leading to a rise in 100+ Gb/s transceiver design and standardization activity. Early 200+ Gb/s serial link components have also been reported using the same PAM4 modulation as 50 and 100Gb/s links. However, the roadmap for electrical links beyond 200Gb/s is less clear. In this talk, time domain modulation (eg PAM4 and above) and frequency domain modulation (eg OFDM) options for next-generation medium-to-long-reach electrical interconnects will be described, with focus on the implications for high-speed ADC and DAC design. Moving forward, cost and yield implications of ever-increasing SoC die size is leading the industry towards system-in-package architectures. To continue bandwidth scaling, dense packaging is required along with highly parallel electrical I/O to interconnect chiplets. Emerging interest in heterogenous integration has ramped up I/O standards activities to enable an industry-wide chiplet ecosystem. We will briefly describe packaging technology to support dense on-module interconnects, and review activity associated with Universal Chiplet Interconnect Express (UCIe), Compute Express Link (CXL), and Bunch of Wires (BoW) interfaces.